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Software Defined Peripherals
07-24-2019, 05:59 PM (This post was last modified: 07-24-2019 06:12 PM by mfleming.)
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Software Defined Peripherals
I happened across an interesting project on Hackaday.io recently that really piqued my interest. I thought I'd post some information about it for those DIY hardware hackers among us who might also be intrigued. The author of the project refers to it as a Software Defined Computer, but to me that means something like simh emulating an Altair 8800 or PDP-8. What the author has done is quite different.

The author started with a legacy microprocessor, in his case an Intel 8085 and a Motorola 68000. For each he then added a modern 32-bit ARM SoC from the STM32 family. The 5V tolerant digital I/O pins of the STM32 are connected to the legacy processor. A program in the STM32 reads the address, status and data lines and responds as though it were memory and peripherals attached to the processor. In the case of the 8085 he emulated memory, a serial interface peripheral, and a programmable timer. The 68000 included the above and a diskette interface emulation so it could run CP/M-68k.

The STM32 can operate in full emulation mode or can be stopped and act as a hardware monitor. Memory can be read or written, disassembled, or hex files can be loaded into memory. The 8085 implementation included two virtual COM devices, one for the emulator and the other for the processor serial device being emulated. Both projects were implemented on a PCB the size of a socket for the legacy microprocessor, and with the STM32 circuitry on the bottom side. All quite impressive! Here are links to the projects.

https://hackaday.io/project/163755-sdc68k
https://hackaday.io/project/163757-sdc85

https://hackaday.io/project/163757/galle...3e52723a52
https://hackaday.io/project/163757/galle...1a2b000fc2

The author provided schematics for both projects but little else. Nothing at all on the software side. I've seen projects where people have built CP/M systems using old legacy parts (or implemented them in an FPGA) but never something quite like this. Implementation calls to mind an RTOS with tasks for emulated devices and interrupt service routines to manage the legacy processor interaction.

I pulled a Teensy 3.5 board from my "toy box" to play around with the idea. It has a Freescale (now NXP) K64 with an ARM Cortex-M4 running at 120 MHz, overclocking to 168 MHz. Timing tests seem to indicate I can run a 6800 at its full 1 MHz speed, generating the clock and accessing the processor lines in 300 ns of the 1000 ns cycle time.

I'm really thinking about taking on a project like this myself. There are still plenty of legacy processors out there, and the software that used to run on them can still be found. I guess it would also give me something new to collect besides calculators Smile

Check out the project!
~Mark

Who decides?
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