HP67 running

[PANAMATIK]

(05-31-2016 10:33 AM)teenix Wrote:  I believe the data stream to/from the cards is about 1KHz with 28 bits of information made available for each transfer. It would therefore take about 28mS for the CRC to shift these into one of its buffers ready to go and this provides a time slot of 28mS for the PIC to read them while the next buffer fills.

Hi Tony,

As you already stated in your next post, the timing is indeed 180kHz, because the card buffer must be read as 56-bit RAM register mapped at $9B from the real CRC chip, and reading RAM must be done serially via the DATA line with 180kHz directly after a data -> c instruction. this is the critical part for the newACT, because its dedicated serial inputs are already used for reading the next instruction at the same time, so I had to map the DATA line to a normal input pin.

But discussion is always very helpful and the more I defend my point of the difficulty of the task, the more I am wrong and see possibilities to get it working though, if I had the next time slot for more experiments.

Bernhard