FRAM71 : Configuration Spreadsheet [2021-01-31]

[Sylvain Cote]

(02-14-2021 12:55 AM)Dave Frederickson Wrote:  After referring to the IDS, I believe all chips in a sequence must be the same size, or more precisely, have the same Chip ID.

I understand that and this is what we are partly seeing, but it seems that what I am trying to convey is not clear, let me try to explain it again, maybe this it will be more clear.

a) if we decide to see each individual chip then MEMBUF in the example #03 should give us the following report:

Code:

|                        |                  |        | ---[ SHOW  PORT ]--- | --------[ MEMBUFF  OUTPUT ]-------- | 
| Test                   | POKE "2C000",... | MEM(5) | Port   Size    Type  | Port  Dev  Seq  Size  Addr   Type   | 
| ---------------------- | ---------------- | ------ | ----  ------  ------ | ----  ---  ---  ----  -----  ------ | 
| #03 → 80 = 32+32+16    | "1314A500"       |  32768 |   5    32768  1:IRAM |   5    0    0    32   E0000  1:IRAM | 
|                        |                  |        |   5    32768  1:IRAM |   5    0    1    32   D0000  1:IRAM | 
|                        |                  |        |   5    16384  1:IRAM |   5    0    2    16   48000  1:IRAM | 
| ---------------------- | ---------------- | ------ | ----  ------  ------ | ----  ---  ---  ----  -----  ------ |

The above option still creates an issue with multiple simultaneous ports 5.00.

b) otherwise if we decide to only see one virtual chip, then MEMBUF in example #03 should give us the following report:

Code:

|                        |                  |        | ---[ SHOW  PORT ]--- | --------[ MEMBUFF  OUTPUT ]-------- | 
| Test                   | POKE "2C000",... | MEM(5) | Port   Size    Type  | Port  Dev  Seq  Size  Addr   Type   | 
| ---------------------- | ---------------- | ------ | ----  ------  ------ | ----  ---  ---  ----  -----  ------ | 
| #03 → 80 = 32+32+16    | "1314A500"       |  81920 |   5    81920  1:IRAM |   5    0    0    80   C0000  1:IRAM | 
| ---------------------- | ---------------- | ------ | ----  ------  ------ | ----  ---  ---  ----  -----  ------ |

Currently we have a split personality behavior,
a) if you define multiple chips of the same size, then the module expose one virtual chip made of multiple FRAM chips, but
b) if you define multiple chips with a mix of size, then the module expose several virtual chips made of multiple sequential FRAM chips of the same size, if any.

We are discussing semantic here, because for sure I can reproduce the 80KB configuration by aggregating five 16KB chips to create one virtual 80KB chip.

The reason I am discussing this issue, is that I want to correctly do the calculations, the ports assignation and the warnings in the spreadsheet to reflect the module behavior as much as possible.

Sylvain

edit: typo