HP-41 instruction print bug found

[Monte Dalrymple]

(11-04-2019 05:52 AM)hth Wrote:  

(11-04-2019 05:17 AM)Monte Dalrymple Wrote:  Physical images plugged into the 41CL always take precedence. So the only way to "patch" the physical HP-IL ROM would be to physically disable (ie remove) the ROM in the HP-IL module and then "PLUG" in a patched version in the 41CL.

Then why do I get a conflict if I plug the HP-IL module into the 41CL without mapping the MMU? YFNZ is in page 7 by default, should it not be shadowed by the HP-IL module in that case?

When an image is plugged in internally the ROM contents (instructions) are driven onto the ISA bus so that anything on the bus can see the instruction stream. In a Turbo mode the ISA bus is driven with NOPs unless a 1X-tagged instruction is fetched on the bus. If a physical module is addressed at the same page it will also try to drive the ISA bus with instructions. This creates a bus fight and anything on the bus (including the CPU) will "see" garbage. This is why a MMU-disabled 41CL will have problems with an HP-IL module being plugged in.

In retrospect, I probably should have designed this differently, so that YFNZ was not driven on the bus while plugged in to Page 7. Oh well.

By the way, the 41CL does handle Page 5 this way, which is why a Time Module can be inserted without a conflict. The internal Page 5 access is recognized by the logic during the address phase on the ISA bus and the address driven on the bus is modified so that it isn't a Page 5 address. So the ROM in the Time Module is never accessed, but everything on the bus sees the instruction stream, just (apparently) at an address in a different page.