Electronic Wizards

[brouhaha]

I should have put the net label CLK_PMOS on the other side of R1.
One can also increase the value of R1 by quite a bit. 1K is fine, above 2.2K it works less well. That reduces the peak current into the FET gates, but makes the FET take longer to turn on, so the current is drawn for a longer time. That's probably better for the clock driver in the calculator (in the ACT chip), but it's still not great, compared to buffering with a CD4xxxB.