Casio 4bit SRAM replacement project

[Jeff_Birt]

When the Casio PB-100 / Tandy PC-4 starts up it does a Read/Write/Read/Write sequence to various RAM locations trying to find out how much RAM is available. It has one 2K byte (arranged as 4bits by 4K) chip on board and you can add one more as an 'option RAM'. The built in chip is Device 0, the option RAM is Device 1 (DEV1), etc.

With only the on board RAM you can see it ping DEV0, then DEV1. Of course it does not get a proper response from DEV1. I just got the handshaking working for emulating DEV1 and was surprised to see it trying to ping DEV2. It was my understanding it could only handle up to DEV1, i.e. a total of 4K bytes of RAM. The screen shot attached is from a program I wrote to decode the output of my LA.

Interestingly even though it gets the proper response from DEV1 at power on it does not show that is has more RAM. I suspect when the master reset it pressed it determines the amount of RAM present and stores that somewhere. The power on ping test may just be a way to confirm the RAM is still present.