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Sylvain Cote · 02-06-2021, 12:58 AM

(02-04-2021 07:27 AM)Hans Brueggemann Wrote: on page 6, it should read "Changed: 16KB chips usage now restricted to BOT FRAM.".
on page 14, table 3 is correct.

Great! that is what Dave told me and what I was expecting.

Here, some questions that I have never asked but has been put in my notes several years ago.
They relates to the physical jumpers and to their improper uses.

FRAM71: if J1 and J2 are inserted at the same time
1. is it harmfull to the hardware ?
2. if no, how the firmware will react to it ?
if J1 and CN2-5 are inserted at the same time
1. is it harmfull to the hardware ?
2. if no, how the firmware will react to it ?
  1. freeze it ?
  2. SYSRAM is active
  3. Hardwire is active
  4. Hardwire is active and part of SYSRAM is active (0x10000 to 0x1FFFF)
if CN2-3 and J1 are inserted at the same time
1. is it harmfull to the hardware ?
2. if no, how the firmware will react to it ? (my take will be that CN2-3 take precedence)
if CN2-3 and CN2-5 are inserted at the same time
1. is it harmfull to the hardware ?
2. if no, how the firmware will react to it ? (my take will be that CN2-3 take precedence)
if CN2-3, J1 and CN2-5 are inserted at the same time
1. is it harmfull to the hardware ?
2. if no, how the firmware will react to it ? (my take will be that CN2-3 take precedence)
More generally, in what order the FPGA code evaluate the jumpers.

Thank you!

Sylvain

Code:

================================================================================​=================

Module   Jumper  State      description

-------  ------  ---------  ---------------------------------------------------------------------

Code:

FRAM71   J2      inserted   SYSRAM Disabled

any      J1      removed    SYSRAM Disabled

-------  ------  ---------  ---------------------------------------------------------------------

FRAM71   J2      removed    SYSRAM Enabled 

any      J1      inserted   SYSRAM Enabled

-------  ------  ---------  ---------------------------------------------------------------------

FRAM71   CN2-1   removed    Bottom FRAM selected (bottom_F_0x00000 to bottom_F_0xFFFFF)

FRAM71   CN2-1   inserted   Top    FRAM selected (   top_F_0x00000 to    top_F_0xFFFFF)

-------  ------  ---------  ---------------------------------------------------------------------

FRAM71B  CN2-1   removed    Bottom FRAM selected (bottom_F_0x00000 to bottom_F_0x2FFFF)

FRAM71B  CN2-1   inserted   Top    FRAM selected (   top_F_0x00000 to    top_F_0x2FFFF)

Code:

any      CN2-2   removed    IRAM mapping enabled

any      CN2-2   inserted   IRAM mapping disabled

-------  ------  ---------  ---------------------------------------------------------------------

any      CN2-3   removed    71B bus write enabled

any      CN2-3   inserted   71B bus write disabled, H_0x2C000 to H_0x2C01F mapped only

-------  ------  ---------  ---------------------------------------------------------------------

any      CN2-4   removed    Disable SYSRAM writing

any      CN2-4   inserted   Enabled writes to F_0x00000...F_0x1FFFF through H_0x00000...H_0x1FFFF

-------  ------  ---------  ---------------------------------------------------------------------

any      CN2-5   removed    Chip 0 behaves normally

any      CN2-5   inserted   Chip 0 is mapped to H_0xE0000