Electronic Wizards

[brouhaha]

A conventional optoisolator would put a LOT of load on the clock. Typical optoisolators require 5mA of input current. Low-current ones (e.g. Toshiba TLP182) still require 0.5mA, which is a lot to put on a MOS clock signal. There are various "digital isolators" using optical, capacitive, or magnetic technology, but they won't work with a >19V input swing.

One could use a buffer that can work on >19V (e.g. CD4049UB or CD4050B, 1uA input current) and have the buffer drive the opto, or any other sort of level shifter that might otherwise present undesirable loading on the PMOS clock. The 4049 and 4050 are only specified for 15V operation, but abs max is 20V, so they should work fine.

Another possibility is using capacitive coupling into a level shifter designed for positive input only, though the level shifter will still have to deal with a 19V input swing, which would usually require a supply voltage of at least 20V.

Maybe buffering with a CD4050B powered by the calculator, and using the output of that to drive a TIA-232 receiver as suggested by Garth Wilson, might be viable, though the prop delay through even a "fast" TIA-232 receiver can be huge.

Or use the CD4050B, put a voltage divider on its output to reduce swing to what's needed (maybe 3V), and capacitively couple that into the modern logic input.

I think I'd stil luse the nFET, though.