How to test memory in an HP48 RAM card

[Jonathan Busby]

(06-04-2019 06:17 PM)mfleming Wrote:  Hi all,

Hope someone might help with this question. After months of scanning TAS for a reasonably priced 128K RAM card for a 48SX/GX, I finally gave up and decided to make my own. Using plans from hpcalc.org and updating the BOM to a Cypress memory device, I managed to assemble a half dozen cards. Each one came up with the initial Invalid Card Data warning, after which I initialized by storing and purging a port variable (HP48SX). All seems well - I can store and recall variables, merge memory, and retain content on battery power when the card is removed from the calculator.

I wonder, does initialization test every byte of the memory on the card? Visual inspection indicates every pin is properly soldered. I'd just like to be sure all is well, and that I haven't left an address line floating or something.

Thanks,
~Mark

Back in 2015 I bought two 128KiB SRAM cards and two 2MiB SRAM cards for two of my three HP48GXs. I got them from Oleg Rodionov who had designed several sizes of SRAM and F-RAM cards and was selling them on eBay. All the cards worked fine until late last year when the 128KiB RAM card that was merged with IRAM in my Indonesian made HP48GX "crapped out" and gave me a TTRM ( Suffice it to say that I was upset because I had a substantial amount of data, mainly source code, saved on that calc and I don't know where my most recent backup is -- I've moved to Colorado and the backup would probably be in an external HDD in storage but it might be weeks before all my possessions are shipped up here ). I used Oleg's "chkmem" which didn't report any errors, *but*, the built in HP48GX self test *did* report an error on the 128KiB RAM card. I'm in correspondence with Oleg and he said it might be a bad solder joint.

So, my recommendation is to use Oleg's "chkmem" as it seems to be very thorough.

NOTE : I'm also currently in the process of designing high capacity ( 2MiB and 4MiB ) F-RAM cards for my HP48GXs using Cypress Semiconductor "Exelon" Ultra Low Power 8Mbit SPI F-RAM chips because they have a 1000 trillion ( one quadrillion ) write endurance. I've had to start designing a serial SPI to parallel SRAM interface ( using an ultra low power PIC12 -- will switch to a Xilinx CPLD or a Microsemi FPGA if the PIC12 MCU solution doesn't work out ) but the timings are tight and I'm not sure if the required clock cycle stretching I need to do will upset the F-RAM chips.

Regards,

Jonathan