|Re: Verilog or VHDL Emulator for HP 16C?|
Message #10 Posted by Monte Dalrymple on 1 Feb 2005, 12:30 p.m.,
in response to message #1 by Bennett Smith
The 16C uses the same CPU as the 41C. What makes it a different machine is the software held in ROM. The specification for the CPU is available on the internet if you know where to look. Unfortunately it is not quite complete, so you have to make some intelligent decisions about how the designers implemented a few things.
Unfortunately, a similar specification is not available (at least that I have found) for the display driver chip. If you are ambitious and have the time, you might be able to figure out how it works by disassembling the 16C ROM code. I expect that it would be similar in many ways to the 41C display driver operation, and that spec is available on the internet.
The CPU is actually quite simple, and only requires 19 pages of Verilog HDL code. As Meindert mentioned in another reply, I am working on an enhanced version of this CPU so that I can do a brain transplant on 41Cs. It wraps additional logic around a Nut CPU core to add a number of new features. A preliminary specification for the NEWT microprocessor can be found at
Unfortunately I haven't had a lot of time to devote to this project since the HHC 2004 conference, but I expect to be able to run my first simulation within the next couple of weeks. Because I will be implementing this in an FPGA the power management will need to be done externally (so that I can power down the FPGA), and I still need to work that out. I intend to make that operation transparent to the user.
The other issue is the different voltage levels involved. The FPGA core runs at 2.5V, the FPGA I/O and memories run at 3.3V, and the 41C bus runs at 6V. I've got the 6V translators designed, but still need to design the power supplies for the remainder of the stuff.
I will post progress reports as I make progress.