The Museum of HP Calculators

HP Forum Archive 09

[ Return to Index | Top of Index ]

HP-9G architecture comments (to Joerg W's prior post)
Message #1 Posted by Bill Wiese on 10 Dec 2002, 8:43 p.m.

Joerg & the gang...

I had occasion awhile back to look at some Sunplus ICs. Some ASICs are 8031/8051 derivatives IIRC, but the databank stuff, etc. seems to be 6502 based! (This was a year ago so I might be fuzzy). If you can get a hex dump of some code I'd know right off the bat - each CPUs object code has a bit of 'rhythm' to it: 6800 looks different from 6502 which looks different than Z80....

I LOVE the old 6502 ;-) Fond memories.

Bill Wiese San Jose, CA

Joerg Woerner wrote: > The new HP 9G looks like a rebadged... what ? > Dismantling the HP 9G reveals a CPU not expected: A > Taiwanesian "Sunplus SPLB30A" ( > intended for Data Bank applications. You'll find more > data here: > . > It is a complete system with 2.5kByte RAM, 96kByte ROM > and the display driver, key scan logic. In the typical > Data Bank a huge RAM (128k Byte..) is added with a serial > Bus. This is the way we are doing calculators since the > Texas Instruments TI-68: Take a cheap microcontroller and > add some software... Greetings from [=] key. Joerg

What is effectively new in uP architecture?,
Message #2 Posted by Vieira, Luiz C. (Brazil) on 10 Dec 2002, 10:05 p.m.,
in response to message #1 by Bill Wiese


this is a general question: what is effectively new after Turing, Von Newman and Harvard architecture? I am trying to figure it out.

Is there anything that we can call as new instead of this ones with a different makeup? I actually would like to know.

I learned how to "assembly" in a Z80, and used 8086, 8051 and (recently) 16F84x. Bill's post called my attention: everything resembles everything in low-level programming. CISC and RISC are more than well sensed when we use a lot of MOV, ADD, ADC, SUB, PUSH, POP, and a few of (senior moment) not so common instructions (forgive-me not finding a good example now). Microcontrollers add a bit of "brand new" sets when dealing with timers, 12-bit coded instructions and the like, but system core is a new implementation.

I just want to mention Transmeta and Crusoe's "morph" translating layer as one innovative design.


Re: What is effectively new in uP architecture?,
Message #3 Posted by Bill Wiese on 11 Dec 2002, 2:26 p.m.,
in response to message #2 by Vieira, Luiz C. (Brazil)

Von Neumann, Harvard, RISC vs CISC concepts etc. have all been around for a long time. Even VLIW concept (very long instruction word) has been around for awhile: there are custom machines where coding is done at the wide-microcode level for parallelism.

On high-end CPUs (Pentiums, etc.) you're going to see more execution units, things like Intel's hyperthreading, etc. You'll prob see extensions to vector-math hardware like MMX (or AltiVec on PowerPC) for more/better/faster math parallelism.

Low-end CPUs/microcontrollers will evolve more by integration with peripherals (onboard flash, more RAM or DRAM, peripherals, etc.) But as overall market grows there will still be huge need for 4- and 8-bit micros.

You might see more regular micros 16 bit and about having some DSP (digital signal processing) features included. Processors w/DSP capabilities offer both saturating or unsaturating (regular) arithmetic, a fast multiplier, and some of the following: fused multiply-accumulate, zero-overhead looping, bit-reversed indexing for FFT speedups, etc.

Bill Wiese San Jose, CA

[ Return to Index | Top of Index ]

Go back to the main exhibit hall