Saturn level 1 vs level 2 instructions

[brouhaha]

Has anyone put together a definitive list of exactly which Saturn instructions were added in "level 1" (1LK7), vs. "level 2" (everything later)?

I had thought that the HP SASM documentation would be a definitive reference, but I've looked at two different versions, and AFAICT they have some have errors and inconsistencies on this matter. The book Customize Your HP-28 by Wlodek Mier-Jedrzejowicz in Appendix D had one of the earliest published descriptions of the 1LK7 extensions, and includes mention of a few instructions that I thought were level 2, and seems to have some confusion over the opcodes.

The SASM documentation references an internal HP engineering document A-1LK7-0005-1 "CPU Hardware Specification". Has a copy of that ever managed to leak out? Or other internal documentation on any of the Saturn chips?

I've been looking at supporting Saturn-based calculators in Nonpareil II, though it's a lower priority than just getting the pre-Saturn models going again. I could just support all level 2 instructions for all models, given that no 71B software should be using level 1 or level 2, and no 18C or 28C code should be using level 2. However, in the interest of simulation accuracy, I'd rather support the correct levels for each model (which implies giving the user a choice between level 0 and level 1 for the 71B).

Also, if anyone has an errata list for the SASM manual, that would be of interest.

Thanks!

[Christoph Giesselink]

(02-21-2024 03:13 AM)brouhaha Wrote:  Has anyone put together a definitive list of exactly which Saturn instructions were added in "level 1" (1LK7), vs. "level 2" (everything later)?

I had thought that the HP SASM documentation would be a definitive reference, but I've looked at two different versions, and AFAICT they have some have errors and inconsistencies on this matter. The book Customize Your HP-28 by Wlodek Mier-Jedrzejowicz in Appendix D had one of the earliest published descriptions of the 1LK7 extensions, and includes mention of a few instructions that I thought were level 2, and seems to have some confusion over the opcodes.

The SASM documentation references an internal HP engineering document A-1LK7-0005-1 "CPU Hardware Specification". Has a copy of that ever managed to leak out? Or other internal documentation on any of the Saturn chips?

I've been looking at supporting Saturn-based calculators in Nonpareil II, though it's a lower priority than just getting the pre-Saturn models going again. I could just support all level 2 instructions for all models, given that no 71B software should be using level 1 or level 2, and no 18C or 28C code should be using level 2. However, in the interest of simulation accuracy, I'd rather support the correct levels for each model (which implies giving the user a choice between level 0 and level 1 for the 71B).

Also, if anyone has an errata list for the SASM manual, that would be of interest.

Thanks!

The easiest way is using the HP-TOOLS sources. The file /sasm/opcodegen.c contain the information with the definitions LEVEL1, LEVEL2, LEVEL3.

These two ocodes are the difference between the 1LF2 (LEVEL0) and 1LK7 (LEVEL1) CPU:

{"PC=(A)" ,OPD_NONE,LEVEL1,4,"808C","","",0,0,0,0,0,0,0,0,OP_NOTREACHED},
{"RSI" ,OPD_NONE,LEVEL1,5,"80810","","",0,0,0,0,0,0,0,0,OP_NOCHGCARRY},

LEVEL2 instructions are included in all later Saturn CPU designs. Finally LEVEL3 are the additional opcodes of the Saturnator engine introduced with the Apple series calculators.

Another source maybe the emulator sources of Emu28 and/or Emu71/Win. In file FETCH.C the LEVEL2 instructions are disabled for decoding (search for 1LK7).

[J-F Garnier]

My reference is the SASM documentation (file dated July 1991).
In some cases it is indeed not fully consistent, maybe because different parts have been written at different times.

For instance, section 6 "Saturn Assembler Format and Mnemonics" correctly distinguishes between the 3 levels 0, 1, 2. In that section, it is clear that the only new level-1 instructions are PC=(A) and RSI. All level-2 new instructions are also clearly identified as such.

On the contrary, section 8 "Mnemonic Dictionary" seems to be older and to come from the HP-71 Hardware IDS (from the corresponding section 4.4). It is quite obvious in the description of the SREQ? opcode that explicitly targets the HP-71B platform. Only the two new 1LK7 opcodes RSI and PC=(A) have been added in that section, and there is no mention of any level-2 opcodes.

And finally section 9 "Alphabetic Mnemonic List" only distinguishes between the HP-71 (level 0) and the 28S/48SX (level 2, so including also the level 1 opcodes).

Regarding errata in the SASM documentation, I've been told that the cycle counts are not always accurate (some are different depending on the chip levels/versions) but I never paid too much attention to this point.

J-F
Edited to correct my 1LF2/1LK7 confusion.

[Christoph Giesselink]

The first time I had a look , I missed it:

Clarke External Reference Specification

5.6 1LT8 CPU/1LK7 DIFFERENCES

p.50/51