What if?

[Joseph_21sv]

(05-18-2016 01:20 AM)Paul Berger (Canada) Wrote:  

(05-17-2016 11:28 PM)Joseph_21sv Wrote:  Paul, how wide an address bus do you mean, as wide or twice as wide as each individual CPU? If twice as wide, I would not expect that the two CPUs would ever need to contend address bus access because each individual CPU would then have exclusive access to an individual slice of the address bus, thus obviating the need for either option.

Ok lets take a hypothetical new system board that has a 32 bit data bus and a 32 bit address bus. 32 bits of address will allow you to access about 4.29E9 memory locations. If as you propose we split both the address and data bus between the two processors, so each processor has 16 bits data and 16 bits address, well 16 bits of address only allows you to access 65.5E3 memory location, yes it would work but that would hardly be adequate for a modern system. Not only that but since this system board is designed for 32 bits of data and 32 bits of address the memory array is going to be laid out as an array of 4.29E9 32 bit words. The word in that is addressed in that array that is being accessed will be the one pointed to by the sum of the bits active on the whole 32 bit address bus, so with what you propose you would have two separate processors providing half of that address word, the result to say the least would be chaotic. For this to work as you propose with a split address and data bus, the memory array would need to be designed so that it could be reconfigured to split the memory into two separate 64K word array, and if someone was designing a system board for a 32 bit processor with a 32 bit address bus, why would they do such a thing?

In the days of the TI TMS9900 and GI CP16x0 processors that your hypothesis assumes to be on the system board of this computer, 131E3 (128 ki) memory locations and a 17 bit address bus would have been plenty to work with. However, even at the time when PCs were transitioning from 16 to 32 bits, the dominant 16 bit systems (i80286 and M68000) had a 24 bit address bus (the M68000 internally had a 32 bit address space, but Motorola had no space to put on the pins for the highest order byte of the address space). If one assumes either of these historically accurate processors on the hypothetical system board, there are then 33.6E6 (32 Mi) memory locations and a 25 bit address bus (with an internal 33 bit address space). In those days, that would have been plenty to work with (the 32 bit ARM2 processor itself only having 26 bit addressing). Even so, I meant that there would be extra logic for encoding addresses to build up an address bus as wide as the sum of those of the individual CPUs. That way only two CPUs are needed to slice up the address bus as wide as the sum of their individual address busses, which I intended to propose that the hypothetical design would involve.