[41] Odd display problem

[emece67]

This is how, I think, is the logic concerning the OS1/OS2 signals of the LCD driver chips.



In STANDBY mode, signal DPWO is high and PWO (CPU driven) is low. The IAF signal of the 1st chip is always high. Thus, the output of gate U1 is high, enabling the astable multivibrator around U0. Pulses generated by this multivibrator reach the internal counters and also the internal counters of the 2nd chip (via OS2), as the three-state buffer U2 is also enabled by IAF. After 9·2^19 (aprox. 4M7) pulses, the driver chips disable, forcing DPWO low, thus disabling the multivibrator and forcing the CPU to drive SYNC low, the system enters SLEEP mode.

In the 2nd chip, the multivibrator is always disabled because its IAF signal is always low. Its multivibrator is also isolated from the internal counters as U2 is disabled. Thus, its internal counters are driven by the OS2 signal coming from the 1st chip and both chips keep synchronized.

In RUN mode the multivibrator is disabled (because PWO is high, thus the output of U1 is low, which disables U0). In this case, OS1 is high because the high level at the output of U0 reaches OS1 thru Rf. As U2 is enabled, OS2 is low.

The Schmitt trigger NAND gate U0, with C2 and Rf, forms an astable multivibrator. The thresholds of U0 are aprox. 2.0 & 4.3 V. Being Vcc aprox 6.3V, the frequency is aprox 0.653/(Rf*C2). In this case this is aprox. 7 kHz. 4M7 pulses of a 7 kHz signal means aprox. 670 seconds, aprox. 11 minutes, the STANDBY timeout.

Finally, in my machine, it seems that the lower input clamp diode of pin OS1 has been damaged by an electrostatic discharge, as there is a (relatively) low impedance when looking into OS1. Such impedance Rc forms a resistive divider with Rf that prevents the gate U0 to drive OS1 above aprox. 0.8V, thus not reaching the threshold levels of U0 and preventing oscillation. Thus, in my machine, the LCD driver chips remain stopped in STANDBY mode, thus blanking the display and preventing the system to enter SLEEP mode. When a key is pressed or the system is running a program, the CPU drives clocks PHI1 & PHI2 and maintains PWO high, in such situation the LCD driver chips use PHI1 & PHI2 to control their internal timings, so the display works.

In a while I'll describe the patch I've applied.