Threaded Mode | Linear Mode

Sylvain Cote · (This post was last modified: 01-20-2021 03:40 PM by Sylvain Cote.)

Hello Mark,

After reading your manual several times, this is what I understand.

Sylvain

Summary:

The module Flash size is 128KB
- The module Flash is divided into 8 blocks (aka chips)
- Each chip has a size of 16KB
Chips are numbered from 0 to 7
- Chip #0 first 8KB address is reserved for module firmware
- Chip #0 last 8KB address can host an optional user's ROM image (called hidden ROM)
- Chips #1 to #7 is available to host user's ROM images
Chip numbers with their associated addresses
- Chip #0 address is 0x00000
  - Chip #0 first 8KB address is 0x00000
  - Chip #0 last 8KB address is 0x02000
- Chip #1 address is 0x04000
- Chip #2 address is 0x08000
- Chip #3 address is 0x0c000
- Chip #4 address is 0x10000
- Chip #5 address is 0x14000
- Chip #6 address is 0x18000
- Chip #7 address is 0x1c000
ROMs
- ROM order follow ROM enumeration (table entry) order
- Expected ROM size are: 16KB, 32KB or 64KB
- Aggregate ROM size is supported (ex: 48KB ROM built by creating a multi-chip configuration: 16KB+32KB or 16KB+16KB+16KB)
- 0xE0000 hard-wired ROM must be flagged as such and assigned to chip 6 and 7
- Chips listed after ROM enumeration has been stopped are ignored, except for chips 6 and 7 when flagged hard-wired ROM
Control Address Values (0x2C000)
- 0 : unmap chips #0 to #7
- 1 : map chips #1 to #7
- 3 : map chips #0 to #7
Configuration Values:
- SIZE : expected chip size
  - 0x0A : 16KB ROM image
  - 0x09 : 32KB ROM image
  - 0x08 : 64KB ROM image
- RESV : reserved
  - 0x00 : not used
- TYPE : supported device type
  - 0x01 : ROM
- CLAS : device class
  - 0x00 : not used
- LAST : last chip in module
  - 0x00 : not the last chip in module
  - 0x08 : last chip in module
- FLAG : ROM enumeration & hard-wired ROM control
  - 0x00 : continue ROM enumeration
  - 0x01 : stop ROM enumeration
  - 0x02 : hard-wired ROM
- ADDR : lookup value, automatically computed by the firmware
  - 0x00 : default value (any value here will be overridden by the module firmware)
- CHIP : chip number (0..7)
Configuration File:

Code:

org 0x1000 ; ROMs enumerated as 16K chips ROM1

Code:

; SIZE, RESV, TYPE, CLAS, LAST, FLAG ADDR CHIP ; Entry info., size, chips #, comment DB 0x0A, 0x00, 0x01, 0x00, 0x08, 0x00, 0x00, 1 ; FORTH 16KB ROM, 16KB, chip 1, module: part 1 of 1, continue ROM enumeration, :PORT(5.00) DB 0x09, 0x00, 0x01, 0x00, 0x08, 0x00, 0x00, 2 ; MATH 32KB ROM, 32KB, chip 2 & 3, module: part 1 of 1, continue ROM enumeration, :PORT(5.01) DB 0x0A, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 4 ; JPC 32KB ROM, 16KB, chip 4, module: part 1 of 2, continue ROM enumeration, DB 0x0A, 0x00, 0x01, 0x00, 0x08, 0x01, 0x00, 5 ; JPC 32KB ROM, 16KB, chip 5, module: part 2 of 2, stop ROM enumeration, :PORT(5.02) DB 0x0A, 0x00, 0x01, 0x00, 0x08, 0x00, 0x00, 5 ; ignored, 16KB, chip 5, (place holder) DB 0x0A, 0x00, 0x01, 0x00, 0x00, 0x02, 0x00, 6 ; FORTH 32KB HDR, 16KB, chip 6, hard-wired: part 1 of 2, 32KB ROM first half, HP-71B address 0xE0000 to 0xE7FFFF DB 0x0A, 0x00, 0x01, 0x00, 0x00, 0x02, 0x00, 7 ; FORTH 32KB HDR, 16KB, chip 7, hard-wired: part 2 of 2, 32KB ROM second half, HP-71B address 0xE8000 to 0xEFFFFF DB 0x00, 0x00, 0x00, 0x0C, 0x02, 0x00, 0x00, 0 ; MMIO address, chip 0,

Code:

org 0x04000 #include forth1b.inc ; load FORTH 16KB ROM image in module address 0x04000 to 0x07FFF org 0x08000 #include math2b.inc ; load MATH 32KB ROM image in module address 0x08000 to 0x0FFFF org 0x10000 #include jpc05.inc ; load JPC 32KB ROM image in module address 0x10000 to 0x17FFF org 0x18000 #include forth1bhrd.inc ; load FORTH 32KB ROM image in module address 0x18000 to 0x1FFFF (hard-wired ROM) end

Edit 1: typos
Edit 2: integrated Mark comments
Edit 3: clarifications