Benchmarks 71B versus 48GX

[Jonathan Busby]

(06-28-2020 07:35 AM)J-F Garnier Wrote:  

(06-28-2020 02:11 AM)Giuseppe Donnini Wrote:  To my knowledge, there was a second instruction added to the 1LK7, namely RSI (Reset Interrupt System) with an opcode of 80810.

Maybe Jean-François Garnier could enlighten us as to how a late-production HP-71B equipped with the 1LK7 would react to the issuance of that instruction, and how, on the other hand, the 1LF2 in a standard HP-71B would internally decode the corresponding opcode?

It's has always been a mystery for me why the RSI is opcode 80810 and not just 8081. Maybe this additional fetched nibble gave more time for the RSI execution? I would be glad to get the opinion of people more expert than me in the Saturn chipsets.

Due to this trailing 0, an attempt to execute RSI on a 1LF2 will probably put the CPU out of sync with the next opcodes.

As for the effect of RSI on a HP-71 with 1LK7, I don't know. Actually I'm not sure of the exact effect of RSI on the 28C.

The SASM doc says:
"This instruction causes CPU to consider any input line (ie
input register bits) presently high as a new interrupt. If
the CPU is presently in the interrupt routine it will wait
for an RTI before vectoring, otherwise the CPU will vector
immediately following the RSI instruction. For a complete
discussion on the interrupt system see the CPU Hardware
Specification (A-1LK7-9005-1). This instruction is not
available on the 1LF2 version of the Saturn CPU."

This description is not fully clear for me, and unfortunately, I don't have access to the 1LK7 CPU Hardware Specification.

J-F

Well, it seems you have found one of the many Saturn "opcode holes" I don't know why the RSI instruction was encoded as 0x80810 -- perhaps HP was planning on adding more opcodes in future Saturn chips but they never got around to it?

Anyway, I don't know about the HP-71B 1LF2 or 1LK7 CPUs, but on the Yorke Saturn it seems that invalid opcodes are just ignored. For example, the following code contains the invalid opcode 0x80811 . I̵f̵ ̵I̵ ̵a̵p̵p̵e̵n̵d̵ ̵a̵ ̵0̵x̵0̵4̵ ̵t̵o̵ ̵t̵h̵e̵ ̵o̵p̵c̵o̵d̵e̵ ̵t̵h̵e̵n̵ ̵t̵h̵e̵ ̵R̵4̵=̵A̵ ̵i̵n̵s̵t̵r̵u̵c̵t̵i̵o̵n̵ ̵i̵s̵ ̵e̵x̵e̵c̵u̵t̵e̵d̵ -- EDIT : Actually, I made an oopsie -- the above invalid opcode with just 0x04 appended is actually SETHEX. If I append 0x104 then it's R4=A , as demonstrated in the following code :

Code:

ASSEMBLE
    NIBASC    /HPHP48-R/
RPL
CODE
    GOSBVL    =SAVPTR
    A=0    W
    R4=A
    LAHEX    0123456789ABCDEF
    NIBHEX    80811104
    A=R4
    P=    15
    GOVLNG    =PUSHhxsLoop
ENDCODE

I've attached an HP48G-R compatible compiled binary of the above code to this message.

( NOTE : The on-calc checksum is # F393h )

Regards,

Jonathan