Extending the precision of Woodstock or Saturn based calculators

[Alejandro Paz(Germany)]

In the repository here there is a Parallel Saturn core, written in verilog. It is still a work in progress. I just coded, after much thought, a pre-fetching BUS controller.
The Parallel Saturn should improve the throughput in three different ways:

Increasing memory bandwidth for fetch: I opted for a 16 bit memory width, some opcodes are 2 nibbles long, 2 optimally positioned opcodes could be fetched at once. This condition is extra checked.

Increasing memory bandwidth for data access: again 16 bit accesses should improve transfers. Alignment issues arise here and read-before-write cycles are needed.

Increasing the width of the ALU path: Using 64 bit registers at once, while limits the maximum frequency on the target FPGA (<10 MHz), should provide abundant improvement on long executing opcodes.

The ALU is mostly coded, the bus controller is partially coded, no data accesses yet. The rest is a rehash of my nibble-serial (but fully working) 1LF2 implementation.

Let's see if I can fully realize this other project . Even at 2 MHz, it should be many times faster than a Yorke, let's see.