[FRAM71] Pre-Production Batch

[Hans Brueggemann]

(03-16-2015 03:51 PM)Dave Frederickson Wrote:  The bottom FRAM works just fine, but the top FRAM doesn't respond to writes to the config address space. I've inspected the soldering work for shorts and loose pins and have found no issues. Any suggestions?

Dave

dave,
from your photos,
1) the FRAM chip is of the correct type and correctly oriented on the board
2) the wire goes to the correct pin CN6:7 on the pcb.
3) the wire goes to the correct pin 6, !CE, on the FRAM chip
4) not clear on picture: make sure that there is no connection between !CE of bottom FRAM and !CE2 on top FRAM

let's see whether there is a problem with the !CE2 signal of the top FRAM.

here is a correct write cycle as measured on V430 during POKE "2C000", "9" with bankswitching enabled.
CD, STR, HP-BUS are signals on the internal HP-71B bus
OE, WE, CE are FRAM control signals at their respective pins, all active LOW
CE2 is chip_enable of the top FRAM, active LOW
   
depending on the resources at hand, you can check the following:
1) with the HP-71B running idle on SYSROM (J1:open, J2:closed), !CE2 must be always logic HIGH (=3.3V), regardless of the bankswitch setting. you can check this with a DVM in DC mode.
2) assuming that you have either an OS- or the dignostic image loaded into SYSRAM of lower FRAM, you can perform the following "dirty test" to verify whether !CE2 is correctly asserted:
a. turn bankswitching on and turn on your HP-71B.
b. measure the voltage at CN6:7 with a DVM. if 3.3V +/- 100mV, then o.k. otherwise, probably fried chip (either FRAM, FPGA, or both)
c. remove J1, insertJ2. do _not_ set OD. this enables the HP-71B to run on SYSROM, but at the same time generates lots of pulses on !CE2, which leads to a measurable DC voltage drop. Correction: remove J2, insert J1
d. measure the voltage at CN6:7 with a DVM. reading should be approx. 3% below the reading at point c.
e. make sure to remove J2 and insert J1 after the test.

if you have a scope, you can of course verify !CE2 according to the above picture at the following pins:
!WE: CN4:16
!OE: CN6-4
!CE: CN4-5
!CE2: CN6-7

if in test 2) the !CE2 isn't getting "busy" with lots of pulses, let me know so i can have a closer look into it.


hans
(edit 2015-03-23: corrected jumper positions in RED)