[FRAM71] Pre-Production Batch

[Dave Frederickson]

(02-07-2015 06:55 PM)Hans Brueggemann Wrote:  In a recent e-mail, Dave Frederickson pointed out to me that it would be nice to be able to access all 512kB of FRAM, by using some sort of bank switching scheme. i find this idea quite intriguing and FRAM71's FPGA still has ample amount of free logic available (as per V.421) to handle such a task. alas... i'm short on ideas of how to implement that to gain maximum use from such a feature. when looking at the used FRAM address space (nibble addresses),
00000-1FFFF is reserved for diagnostic/alternate O/S,
20000-2BFFF is unused,
2C000-2C01F is reserved for Memory Configuration,
2C020-2FFFF is unused,
30000-FFFFF is reserved for the 0..12 configurable Memory Chips.
that gives basically the range 20000-2BFFFF as a possible candidate for bankswitching.
so, what can we do with that? is it worth a try in the light of the amount of FRAM already available?
what's your take on this, valued users?

It's not the system address space I was suggesting be utilized, but the FRAM memory itself. Currently the 512k FRAM is divided into 16-32k "Chips", 13 of which are available for configuration as RAM or (truly write-protected) ROM. Two are reserved for the SYSRAM feature and the last is unused. What I'm suggesting is that another configuration register, like the 0x2C000 register, perhaps at address 0x2C020, but only 16 bits in length, be created. Each bit would correspond to a 32k Chip in FRAM and if set, that Chip would be "Enabled". The rules would be:

1. Up to 13 bits can be set at one time, corresponding to Chips 12 - 0.
2. The two least significant bits are reserved for SYSRAM and are always zero
   

By manipulating the bits the "active" Chips can be switched making different ROM configurations possible without reloading an image. It should be possible to load an alternate O/S into the 64k SYSRAM and configure the other 14-32k Chips into RAM or ROM.

For example, if 0x2C020 is loaded with 0xF000 and that would enable the 0xF0000 block of FRAM. This would be mapped into Chip 12 and 32k ROM1 could be load into it. If 0x2C020 were loaded with 0x8000 that would enable the 0xE0000 block of FRAM and 32k ROM2 could be load into it. The significant difference is that the set bits in 0x2C020 determine which blocks of FRAM get mapped to Chips, so 0xE0000 become Chip 12, also. By manipulating the bit in 0x2C020 either ROM1 or ROM2 can be enabled.

Another example, load 0x2C020 with 0xFFF8 enabling 13 blocks of FRAM starting at 0x30000 and load 0x30000 with ROM1. Load 0x2C020 with 0xFFFB enabling 13 blocks of FRAM starting at 0x20000 with the 32k block at 0x30000 disabled. Memory at 0x20000 gets mapped to Chip 0 and ROM2 can get loaded into FRAM at 0x20000. Now 14-32k blocks of FRAM can be utilized for RAM or ROM, with the limitation of only 13 of those being enabled at one time.

The FRAM configuration registers at 0x2C000 would need to be moved to the NVRAM in the FPGA, if they're not already there.

Does that make sense? It's important to understand that FRAM memory would get mapped to Chips which then get mapped to 71B address space by the 71's O/S during the power-on memory configuration.

Dave