FRAM71 : Configuration Spreadsheet [2021-01-31]

[Hans Brueggemann]

FRAM71: if J1 and J2 are inserted at the same time, is it harmfull to the hardware ?
THIS IS HARMFULL and WILL DAMAGE YOUR HP-71B.
See the “Nashville” 2015 manual or any manual prior to “Denver” 2016, chapter 7.x. This was one reason why FRAM71 got a redesign into FRAM71B.

if J1 and CN2-5 are inserted at the same time, is it harmfull to the hardware ?
No, not at all harmfull, but may slightly increase current consumption.

if no, how the firmware will react to it?
freeze it ?
No

Hardwire is active and part of SYSRAM is active (0x10000 to 0x1FFFF) ?
yes, but not visible to your HP-71B. This situation causes both FRAM71(B) and HP-71B to simultaneously access the memory bus, but FRAM71(B) bus outputs are designed to be weaker than the HP-71B’s bus drivers. Hence, HP-71B always “wins”.

if CN2-3 and J1 are inserted at the same time
is it harmfull to the hardware ?
No

if no, how the firmware will react to it ? (my take will be that CN2-3 take precedence)
see “Nashville” chapter 7.3, “Denver” chapter 8.3

if CN2-3 and CN2-5 are inserted at the same time
is it harmfull to the hardware ?
No
if no, how the firmware will react to it ? (my take will be that CN2-3 take precedence)
Yes

if CN2-3, J1 and CN2-5 are inserted at the same time
is it harmfull to the hardware ?
No
if no, how the firmware will react to it ? (my take will be that CN2-3 take precedence)
Yes

More generally, in what order the FPGA code evaluate the jumpers.
CN2-3 always takes precedence.