Podalirius,
I just tried my procedure and it worked successfully, the first time and without any error.
Again, I am assuming that you have a properly configured 16K HePaX RAM block located at 0x808 to 0x80B.
If that is not the case then it will not work!
Below is the same procedure as above but with validation point along the way:
Code:
MMUDIS // disable MMU
MMUCLR // clear MMU configuration Set 0
"YFNX" // 41CL Extreme Functions
PLUGH // plug YFNX module to page 0x7
"YFNF" // 41CL Memory Functions
PLUG1L // plug YFNF module to page 0x8
MMUEN // enable MMU
Code:
CAT 2 // should display // IMAG:XR
// -TIME 3A // TMOD:26 at page 0x5
// -CL TIME // XFN5:-- at page 0x5
// -YFNX 4C // YFNX:21 at page 0x7
// -SYS FNS // YFNX:-- at page 0x7
// -SER FNS // YFNX:-- at page 0x7
// -MISC FNS // YFNX:-- at page 0x7
// -YFNF 3A // YFNF:16 at page 0x8
// -EXT FNC 3B // XFN3:25 at page 0x3
// -CL EXT FNC // XFN5:-- at page 0x5
Load MMU secondary configuration table with default values and load set 4 into set 0
Code:
CFGINI // copy MMU configurations from ROM to RAM
RCLCFG 4 // copy MMU configuration from set 4 (9PWR) to set 0
Code:
CAT 2 // should display // IMAG:XR
// -EXT FNC 3B // XFN3:25 at page 0x3
// // 4LIB:-- at page 0x4
// -CL EXT FNC // XFN5:-- at page 0x5
// -TIME 3A // TMOD:26 at page 0x5
// -CL TIME // XFN5:-- at page 0x5
// -AMC"OS/X // OSX3:05 at page 0x6
// -OSX BANK2 // OSX3:-- at page 0x6
// -YFNX 4C // YFNX:21 at page 0x7
// -SYS FNS // YFNX:-- at page 0x7
// -SER FNS // YFNX:12 at page 0x7
// -MISC FNS // YFNX:-- at page 0x7
// -PWRCL EXT // PWRX:-- at page 0x8
// -SYS/EXT // PWRX:15 at page 0x8
// -SI // PWRX:-- at page 0x8
// -WARP CORE+ // WARP:-- at page 0x9
// -STKT // WARP:-- at page 0x9
// -CLXMEM 2E // XPMM:20 at page 0xA
// -YFNM BCKUP // XPMM:-- at page 0xA
// -STKSWP // XPMM:-- at page 0xA
// -Y-REGS FNS // XPMM:-- at page 0xA
// -TOOLBOX"4 // 4TBX:13 at page 0xB
// -HACKER LAB // 4TBX:-- at page 0xB
// -XROM ROM // ROMX:31 at page 0xC
// ->>\/\/>> // ROMX:-- at page 0xC
// -XROM RAM // ROMX:-- at page 0xC
// -HEPAX'4H // HEP2:07 at page 0xD
Swapping WARP and YFNX ROM position and unmap pages 0xB to 0xF
Code:
MMUDIS // disable MMU
"WARP" // WARP ROM (1 page 3 banks)
PLUGH // mapping WARP ROM to page 0x7
"YFNX" // 41CL Extreme Functions
PLUG1U // mapping YFNX ROM to page 0x9
// now just to be on the safe side
UPLUG2U // unmapping ROM from page 0xB
UPLUG3 // unmapping ROMs from pages 0xC and 0xD
UPLUG4 // unmapping ROMs from pages 0xE and 0xF
MMUEN // enable MMU
Code:
CAT 2 // should display // IMAG:XR
// -EXT FNC 3B // XFN3:25 at page 0x3
// // 4LIB:-- at page 0x4
// -CL EXT FNC // XFN5:-- at page 0x5
// -TIME 3A // TMOD:26 at page 0x5
// -CL TIME // XFN5:-- at page 0x5
// -AMC"OS/X // OSX3:05 at page 0x6
// -OSX BANK2 // OSX3:-- at page 0x6
// -WARP CORE+ // WARP:21 at page 0x7
// -STKT // WARP:-- at page 0x7
// -PWRCL EXT // PWRX:12 at page 0x8
// -SYS/EXT // PWRX:-- at page 0x8
// -SI // PWRX:-- at page 0x8
// -YFNX 4C // YFNX:15 at page 0x9
// -SYS FNS // YFNX:-- at page 0x9
// -SER FNS // YFNX:-- at page 0x9
// -MISC FNS // YFNX:-- at page 0x9
// -CLXMEM 2E // XPMM:20 at page 0xA
// -YFNM BCKUP // XPMM:-- at page 0xA
// -STKSWP // XPMM:-- at page 0xA
// -Y-REGS FNS // XPMM:-- at page 0xA
Note: the reason we are doing the above step is that you have mentionned that you want to use set 0x4 (9PWR) without HP-IL module and set 0xF (9HIL) with HP-IL module.
Now, to make the transition easy as possible, YFNX in set 0x4 must be in the same position as YFNX in set 0xF.
Map HePaX RAM & ROM => Warning: The following will fail if your HePaX RAM is not properly configured!
Code:
"%808 C" // based on your previous message your HePaX RAM is from 0x808 to 0x80B
PPLUG // activating HePaX RAM area from page 0xC to 0xF
"HEP2 B" // HePaX 4H ROM (1 page 4 banks)
PPLUG // mapping HePaX ROM to page 0xB
Code:
CAT 2 // should display // IMAG:XR
// -EXT FNC 3B // XFN3:25 at page 0x3
// // 4LIB:-- at page 0x4
// -CL EXT FNC // XFN5:-- at page 0x5
// -TIME 3A // TMOD:26 at page 0x5
// -CL TIME // XFN5:-- at page 0x5
// -AMC"OS/X // OSX3:05 at page 0x6
// -OSX BANK2 // OSX3:-- at page 0x6
// -WARP CORE+ // WARP:21 at page 0x7
// -STKT // WARP:-- at page 0x7
// -PWRCL EXT // PWRX:12 at page 0x8
// -SYS/EXT // PWRX:-- at page 0x8
// -SI // PWRX:-- at page 0x8
// -YFNX 4C // YFNX:15 at page 0x9
// -SYS FNS // YFNX:-- at page 0x9
// -SER FNS // YFNX:-- at page 0x9
// -MISC FNS // YFNX:-- at page 0x9
// -CLXMEM 2E // XPMM:20 at page 0xA
// -YFNM BCKUP // XPMM:-- at page 0xA
// -STKSWP // XPMM:-- at page 0xA
// -Y-REGS FNS // XPMM:-- at page 0xA
// -HEPAX'4H // HEP2:07 at page 0xB
// // hram-p1 at page 0xC
// // hram-p2 at page 0xD
// // hram-p3 at page 0xE
// // hram-p4 at page 0xF
HEPDIR // should display: "H:DIR EMPTY" with 2610 in X (if empty of course)
Save updated set 0 configuration to set 4
Code:
STOCFG 4 // copy MMU configuration from set 0 to set 4 (9PWR)
Warning: using CFGINI after that step will erase the updated set 4 configuration and replace it with its default values.
or save updated set 0 configuration to set 1 (not overwritten by CFGINI)
Code:
STOCFG 1 // copy MMU configuration from set 0 to set 1 (9CFA)
Sylvain
edit1: typo
edit2: add save to configuration 1