41CL: Second set of Extended Memory
04-25-2014, 11:32 AM (This post was last modified: 04-25-2014 01:41 PM by Ángel Martin.)
Post: #1
 Ángel Martin Senior Member Posts: 1,380 Joined: Dec 2013
41CL: Second set of Extended Memory
You probably know already that the 41CL has 2MB of flash and 512kB of RAM capacity. Perhaps the most intriguing aspect of that additional RAM memory would be to make it somehow available to the OS; exceeding the built-in limits of the original design...

No doubt that would require patching the OS extensively, probably too much for a reasonable undertaking and a lot of effort to say the least.

But a lower-hanging fruit could be extending the Extended Memory capacity, definitely more tractable than the main memory space. With that idea in mind I've been fumbling with the X-Mem control and linking registers, trying to add additional EM-blocks to the "chain"; and exploring alternate EM configurations in RAM locations above 0x400.

So far the obvious tricks haven't been fruitfull, it appears there too patching the OS code would be required to get it to work. But using a bit of lateral thinking it's easy to come up with easy ways to back up all your X-memory, or even to have an alternative (dual) set of X-Mem configured, so you can switch back and forth between them.

Below is the quick and dirty FOCAL program to hot-swap the standard X-Memory configuration with another one located in the higher memory locations, above 0x400. It keeps the same structure (one base block of 128 registers plus two additional ones of 239 each), at equivalent addresses to maintain the parity. This maintains the compatibility for main-RAM back-ups as well, assuming of course that the switching routine would be running from ROM.

Interestingly it only uses PEEKR and POKER as non-standard functions, available in the CCD Module and a few of its derivatives.

Take it for a spin and report issues or ideas for enhancement, let's see where can this be taken to...

Code:
 1    LBL "XMSWAP"     2    "BASE"    provide feedback 3    AVIEW     4    128    number of base registers 5    STO M    store counter in M 6    64    origin 7    XEQ 00    swap block 8    "EM-1"    provide feedback 9    AVIEW     10    239    number of base registers 11    STO M    store counter in M 12    513    origin 13    XEQ 00    swap block 14    "EM-2"    provide feedback 15    AVIEW     16    239    number of base registers 17    STO M    store counter in M 18    769    origin 19    LBL 00    swap block 20    CF 00     21    RCL X    origin 22    1024    offset address 23    +    destination 24    LBL 01     25    PEEKR    read destination value 26    X<> Z     27    PEEKR    read source value 28    R^    lift for compare 29    X=Y?    are they equal? 30    SF 00    flag it so 31    RDN    undo lift 32    FS?C 00    equal values? 33    GTO 02    yes, skip writing 34    X<> T    position them crossed 35    POKER    write them back 36    RDN     37    X<> Z    position them crossed 38    POKER    write them back 39    LBL 02    merge code 40    RDN    locate addreses in X, Y 41    E     42    ST+ Z    increase adr-1 43    +    increase adr-2 44    DSE M    decrease counter 45    GTO 01    loop back if not done 46    "DONE"    block is done 47    AVIEW     48    END

Cheers,
ÁM

PS. Slightly improved code updated
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