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+--- Thread: Time Module clone - first light (/thread-8707.html)
Time Module clone - first light - Monte Dalrymple - 07-20-2017 11:23 PM
I finally worked up the courage to program the FPGA eval board and plug it into one of my 41CLs. A lot of things don't work yet, but it keeps time while the calculator is turned on...
Here's a picture:
http://www.systemyde.com/jpg/FIRST_LIGHT.JPG
RE: Time Module clone - first light - Sylvain Cote - 07-21-2017 01:04 AM
Great!
I just received 6 x HP-82106A memory modules to host your time modules.
Sylvain
RE: Time Module clone - first light - Ángel Martin - 07-21-2017 05:14 AM
Nice looking baby, this is a challenging project - the TIME module has much more than meets the eye, serious underpinnings!
Looking forward to the next stages...
RE: Time Module clone - first light - Sadsilence - 07-21-2017 06:28 AM
First good message of the day after reading newspaper this morning (in Middle Europe) :-).
RE: Time Module clone - first light - aurelio - 07-21-2017 10:19 AM
(07-21-2017 06:28 AM)Sadsilence Wrote: First good message of the day after reading newspaper this morning (in Middle Europe) :-).
RE: Time Module clone - first light - Dieter - 07-21-2017 08:16 PM
(07-20-2017 11:23 PM)Monte Dalrymple Wrote: Here's a picture:
While we're talking about time and date:
Monte, maybe you should check your camera clock. ;-)
Dieter
RE: Time Module clone - first light - Monte Dalrymple - 07-21-2017 09:48 PM
(07-21-2017 05:14 AM)Ángel Martin Wrote: Nice looking baby, this is a challenging project - the TIME module has much more than meets the eye, serious underpinnings!
Looking forward to the next stages...
The trickiest part is switching the clocks around when the 41 powers up or down, because you have to keep time across the transition and then while power is down. It looks like that is working fine, from what I've seen today.
The accuracy factor might seem tricky, and it is done in a very clever way, but it's clearly described in the HP documentation.
Debugging is VERY slow-going, because I can only look at a couple of internal signals at a time, and I have to recompile the design each time I change a signal I want to look at. Speaking of which, is there any existing software that will let me peek and poke 41C peripheral registers? The peek and poke functions that I wrote for the CL only work with CL peripheral registers, and It would be really nice to be able to directly access the timer registers while I'm debugging.
RE: Time Module clone - first light - Ángel Martin - 07-22-2017 06:43 AM
(07-21-2017 09:48 PM)Monte Dalrymple Wrote: Debugging is VERY slow-going, because I can only look at a couple of internal signals at a time, and I have to recompile the design each time I change a signal I want to look at. Speaking of which, is there any existing software that will let me peek and poke 41C peripheral registers? The peek and poke functions that I wrote for the CL only work with CL peripheral registers, and It would be really nice to be able to directly access the timer registers while I'm debugging.
My first thought is just enabling the Time module ([ENTMR] at 0x50E2) and use the same code you have to access registers on the CL chip. I don't remember how many registers does the Time module have, but that"s documented somewhere (I think you already have those; reading some of your previous posts).
PS. Just checked Poul Kaarup's "programmers handbook", which has a very nice summary in pages #22 & #23