A LANGUAGE FOR DIGITAL DESIGN - Thomas Klemm - 03-01-2019 04:55 AM
Quote:The point I want to emphasize is the ease with which a new arithmetic can
be defined using the post-fix nature of the FORTH interpreter, and the
readability of the resulting equations.
-- Chuck Moore
Based on A LANGUAGE FOR DIGITAL DESIGN I wrote these programs for the HP-48GX.
A signal has bit 15 on (+5V) or off (GND) .
Bits 14-0 hold the time it becomes known (ns or .1ns).
# 32768d == # 8000h
# 32767d == # 7FFFh
Digital logic simulator
S. types the value and time of a signal (+ indicating +5V).
Code:
« DUP # 32767d AND
IF # 32768d ROT OVER AND ==
THEN "+" →TAG
END
»
¬ complements a signal (without changing its time).
max returns the maximum of two binary numbers.
Code:
«
IF DUP2 <
THEN SWAP
END DROP
»
and combines 2 signals with worst case timing.
Code:
« OVER # 23767d AND
OVER # 23767d AND
max
ROT # 32768d AND
ROT # 32768d AND
AND +
»
or combines 2 signals using DeMorgan's law.
Technology
AND2¬ is a 2-input nand gate with 9ns delay.
OR3 is a 3-input or gate with 30ns delay.
XOR2 is a 2-input exclusive-or gate with 35ns delay.
Code:
« OVER ¬ OVER and
SWAP ¬ ROT and
or # 35d +
»
Logic equations
A is a signal known low at 0ns.
B is a signal known low at 10ms.
C is a signal known high at 10ms.
ENB¬ is a signal determined low by A and B at 45ns.
XY is a signal determined high by A, B and C at 84ns.
Code:
« ENB¬ C AND2¬ A B OR3 »
Examples
ENB¬
S.
# 45d
XY
S.
+: # 84d
Kind regards
Thomas
HP-42S: A LANGUAGE FOR DIGITAL DESIGN - Thomas Klemm - 03-01-2019 03:14 PM
Here are the equivalent programs for the HP-42S.
A slightly different data-format is used though: s.tttttt
s: signal on (1) or off (0)
tttttt: time in ns
Digital logic simulator
Code:
00 { 55-Byte Prgm }
01▸LBL "_"
02 FP
03 1
04 LASTX
05 IP
06 -
07 +
08 RTN
09▸LBL "and"
10 FP
11 X<>Y
12 LASTX
13 X<>Y
14 AND
15 X<>Y
16 LASTX
17 FP
18 X>Y?
19 X<>Y
20 R↓
21 +
22 RTN
23▸LBL "or"
24 XEQ "_"
25 X<>Y
26 XEQ "_"
27 XEQ "and"
28 XEQ "_"
29 END
Technology
Code:
00 { 91-Byte Prgm }
01▸LBL "2AND_"
02 XEQ "and"
03 XEQ "_"
04 9ᴇ-6
05 +
06 RTN
07▸LBL "3OR"
08 STO 00
09 R↓
10 XEQ "or"
11 RCL 00
12 XEQ "or"
13 3ᴇ-5
14 +
15 RTN
16▸LBL "2XOR"
17 STO 00
18 XEQ "_"
19 X<>Y
20 STO 01
21 XEQ "and"
22 STO 02
23 RCL 00
24 RCL 01
25 XEQ "_"
26 XEQ "and"
27 RCL 02
28 XEQ "or"
29 35ᴇ-6
30 +
31 END
Logic equations
Code:
00 { 54-Byte Prgm }
01▸LBL "ENB_"
02 RCL "A"
03 RCL "B"
04 XEQ "2XOR"
05 RTN
06▸LBL "XY"
07 XEQ "ENB_"
08 RCL "C"
09 XEQ "2AND_"
10 RCL "A"
11 RCL "B"
12 XEQ "3OR"
13 END
Examples
0.000000
STO "A"
0.000010
STO "B"
1.000010
STO "C"
XEQ "ENB_"
0.000045
XEQ "XY"
1.000084
Cheers
Thomas
Python: A LANGUAGE FOR DIGITAL DESIGN - Thomas Klemm - 03-05-2019 10:22 PM
Python Code
Code:
def S(x):
'''types the value and time of a signal (+ indicating +5V).'''
t = x & 0x7FFF
return "+" + str(t) if x & 0x8000 else str(t)
def _(a):
'''complements a signal (without changing its time).'''
return a ^ 0x8000
def AND(a, b):
'''combines 2 signals with worst case timing.'''
return max(a & 0x7FFF, b & 0x7FFF) + (a & b & 0x8000)
def OR(a, b):
'''combines 2 signals using DeMorgan's law.'''
return _(AND(_(a), _(b)))
def AND2_(a, b):
'''is a 2-input nand gate with 9ns delay.'''
return _(AND(a, b)) + 9
def OR3(a, b, c):
'''is a 3-input or gate with 30ns delay.'''
return OR(OR(a, b), c) + 30
def XOR2(a, b):
'''is a 2-input exclusive-or gate with 35ns delay.'''
return OR(AND(a, _(b)), AND(_(a), b)) + 35
A = 0 # is a signal known low at 0ns.
B = 10 # is a signal known low at 10ms.
C = _(10) # is a signal known high at 10ms.
def ENB_():
'''is a signal determined low by A and B at 45ns.'''
return XOR2(A, B)
def XY():
'''is a signal determined high by A, B and C at 84ns.'''
return OR3(AND2_(ENB_(), C), A, B)
Python REPL
Code:
>>> S(ENB_())
'45'
>>> S(XY())
'+84'
Clojure: A LANGUAGE FOR DIGITAL DESIGN - Thomas Klemm - 03-05-2019 10:25 PM
Clojure Code
Code:
(defn S
"types the value and time of a signal (+ indicating +5V)."
[x]
(let [t (bit-and 0x7FFF x)]
(if (zero? (bit-and 0x8000 x))
(str t)
(str "+" t))))
(defn _
"complements a signal (without changing its time)."
[a]
(bit-xor a 0x8000))
(defn AND
"combines 2 signals with worst case timing."
[a b]
(+ (max
(bit-and a 0x7FFF)
(bit-and b 0x7FFF))
(bit-and
(bit-and a 0x8000)
(bit-and b 0x8000))))
(defn OR
"combines 2 signals using DeMorgan's law."
[a b]
(_ (AND (_ a) (_ b))))
(defn AND2_
"is a 2-input nand gate with 9ns delay."
[a b]
(+ (_ (AND a b)) 9))
(defn OR3
"is a 3-input or gate with 30ns delay."
[a b c]
(+ (OR (OR a b) c) 30))
(defn XOR2
"is a 2-input exclusive-or gate with 35ns delay."
[a b]
(+ (OR (AND a (_ b)) (AND (_ a) b)) 35))
(def A 0) ; is a signal known low at 0ns.
(def B 10) ; is a signal known low at 10ms.
(def C (_ 10)) ; is a signal known high at 10ms.
(defn ENB_
"is a signal determined low by A and B at 45ns."
[]
(XOR2 A B))
(defn XY
"is a signal determined high by A, B and C at 84ns."
[]
(OR3 (AND2_ (ENB_) C) A B))
Clojure REPL
Code:
user=> (S (ENB_))
"45"
user=> (S (XY))
"+84"
|