[41CL WARP] XEQ+ oddness
04-10-2021, 12:33 AM
Post: #21
 cdmackay Senior Member Posts: 634 Joined: Sep 2018
RE: [41CL WARP] XEQ+ oddness
I repeated the test, including OSX3 but omitting PWRX, and all is fine: the problem is gone.

i.e. with:

Code:
-820 4 OSX3 8 *821 B

all is fine.

Repeated again, this time including PWRX, and omitting OSX3, and the problem returns.

i.e. with

Code:
-820 4 PWRX A *821 B

the problem returns; XEQ+ 'Q':

Code:
"Q       385

So it looks like the presence of PWRX is required, to cause the problem.

Cambridge, UK
41CL/DM41X 12/15C/16C DM15/16 71B 17B/BII/bII+ 28S 42S/DM42 32SII 48GX 50g 35s 30b/WP34S Prime G2
& Casios, Rockwell 18R :)
04-10-2021, 06:21 AM
Post: #22
 Ángel Martin Senior Member Posts: 1,263 Joined: Dec 2013
RE: [41CL WARP] XEQ+ oddness
Well, this is rather strange, let's see... the only thing we haven't tried so far is to double-check the Library#4 itself. Can you try with the attached one and see if that was the root cause?

If you execute CAT'0 - then press "G" you should see the following for the Library#4 entry:

4:-LIB#4 R58b. (the b won't show on the CL)

Normally I'm very disciplined sending all updated to Monte but I could have slipped something the last time, so the best way to tell is by trying the attached one.

Attached File(s)
04-10-2021, 10:47 AM (This post was last modified: 04-10-2021 01:46 PM by Sylvain Cote.)
Post: #23
 Sylvain Cote Senior Member Posts: 1,717 Joined: Dec 2013
RE: [41CL WARP] XEQ+ oddness
I am getting the same result with the same setup.

I have loaded the new LIBRARY4 at page 825 then remapped page 4 from 820 to 825.
No change, same result.

Setup #1
Code:
-825 4 OSX3 8 YFNX 9 *821 B XEQ+ 'Q' → XEQ"QREM
... working

Setup #2
Code:
-825 4 YFNX 9 PWRX A *821 B XEQ+ 'Q' → "Q       385"
... not working

Setup #3
Code:
-825 4 OSX3 8 YFNX 9 PWRX A *821 B XEQ+ 'Q' → "Q       385"
... not working

Modified setup #3
Code:
EMPT A XEQ+ 'Q' → XEQ"QREM
... working

Unmodified setup #3 catalog listing (CAT"0 G) on thermal printer (82143A) in TRACE mode:
Code:
3:-EXT FCN 3B 4:-LIB#4 R58b. 5:-TIME  3B 6:-PRINTER- 7: NO ROM 8:-OSX BANK2 9:-YFNX 4C A:-PWRCL EXT B:-WARP CORE+ C:-SNDMTH'4X4 D:-HL MATH+ E: NO ROM F: NO ROM

04-10-2021, 04:10 PM (This post was last modified: 04-10-2021 04:31 PM by Ángel Martin.)
Post: #24
 Ángel Martin Senior Member Posts: 1,263 Joined: Dec 2013
RE: [41CL WARP] XEQ+ oddness
Thanks to both for the testing, so now we're on the same page and you two are seeing the same problem so there's got to be something intrinsically wrong in there. I've configured my CL using the same ports and the issue also happens - finally - on my system. I typically plug the PWRX in page#7, I guess that's why this didn't ever come up for me.

Looking at the choice of pages I believe the standard bank-switching behavior is the root cause of the problem. Notice that both pages #A and #B will bank-switch together, i.e. it happens at the PORT level. This is so that dual-page modules (like the HP41 Advantage) work OK during the bank-switched calls.

So what happens when both the PWRX and the WARP are in the same "port" (pages #A and #B) is that they'll both switch banks together. This is bad because the WARP code will instruct the PWRX to switch banks looking for auxiliary FATS in it. When it does, the execution returns to the WARP to read the aux-FAT contents - but alas, WARP is also in a different bank so the execution returns to la-la-land, and hence the screw-up/

The solution: never plug the WARP together (in a port) with another single-page, bank-switched module such as PWRX, OSX3, 16CS... and the problem won't occur.

Note that two-page bank-switched modules (like SandMath, SandMatrix, 41Z, etc.) could also show this problem if you plug them in a port-straddled configuration (upper page of lower port and lower page of upper port). This of course is not possible in the real machine or V41/41X but on the CL the flexibility is total so it's possible to do it.

So the proof is in the pudding: simply plug the WARP in a port without other B-S module and try again. I'd strongly recommend using page#7 for either PWRX or WARP, assuming of course that no HP-IL is needed.

And the verdict is...
04-10-2021, 06:35 PM (This post was last modified: 04-10-2021 06:35 PM by cdmackay.)
Post: #25
 cdmackay Senior Member Posts: 634 Joined: Sep 2018
RE: [41CL WARP] XEQ+ oddness
Excellent! thanks very much, Ángel. That has fixed it, indeed.

Code:
4LIB 4 OSX3 8 PWRX A WARP C

all from the 4/4/2021 set, works fine.

Marvellous!

Cambridge, UK
41CL/DM41X 12/15C/16C DM15/16 71B 17B/BII/bII+ 28S 42S/DM42 32SII 48GX 50g 35s 30b/WP34S Prime G2
& Casios, Rockwell 18R :)
04-10-2021, 06:43 PM (This post was last modified: 04-10-2021 06:48 PM by cdmackay.)
Post: #26
 cdmackay Senior Member Posts: 634 Joined: Sep 2018
RE: [41CL WARP] XEQ+ oddness
I keep pages 6 & 7 free for HP-IL, on my 41CL, which is why I've run into this.

I'm not quite clear on the rule we should follow; is it:

• do not mix two different single-page bank-switched modules in a single port

or

• do not mix anything with a single-page bank-switch module in a single port. i.e. leave the other page empty, in that port

i.e. is it OK to have:

page A — single-page bank-switched module
page B — single-page non-banked module

or would A switching also upset B, even if B isn't itself bank-switched?

[Also, do we know if the DM41X auto-plugging selection rules take this into account?]

Cambridge, UK
41CL/DM41X 12/15C/16C DM15/16 71B 17B/BII/bII+ 28S 42S/DM42 32SII 48GX 50g 35s 30b/WP34S Prime G2
& Casios, Rockwell 18R :)
04-10-2021, 06:45 PM
Post: #27
 cdmackay Senior Member Posts: 634 Joined: Sep 2018
RE: [41CL WARP] XEQ+ oddness
So, thank you very much Ángel, for the solution.

And thanks very much also to Sylvain, for taking the time to reproduce, and demonstrate that I wasn't imagining it all

Cambridge, UK
41CL/DM41X 12/15C/16C DM15/16 71B 17B/BII/bII+ 28S 42S/DM42 32SII 48GX 50g 35s 30b/WP34S Prime G2
& Casios, Rockwell 18R :)
04-10-2021, 08:03 PM (This post was last modified: 04-10-2021 08:06 PM by rprosperi.)
Post: #28
 rprosperi Senior Member Posts: 5,069 Joined: Dec 2013
RE: [41CL WARP] XEQ+ oddness
Nice detective work Angel!

Was this fact, that adjacent Pages in a given Port both bank-switch together well-known or is this a new discovery? And of course by 'well-known' I mean by you gurus, not the rest of us heathens....

(04-10-2021 06:43 PM)cdmackay Wrote:  [Also, do we know if the DM41X auto-plugging selection rules take this into account?]

I believe (Angel, please correct me if I'm wrong) this doesn't occur on the 41X because the adjacent Pages in a common Port are not physically connected so the bank switch for one does not affect the other (one advantage of s/w based emulation )

--Bob Prosperi
04-10-2021, 08:39 PM (This post was last modified: 04-10-2021 08:49 PM by Sylvain Cote.)
Post: #29
 Sylvain Cote Senior Member Posts: 1,717 Joined: Dec 2013
RE: [41CL WARP] XEQ+ oddness
(04-10-2021 08:03 PM)rprosperi Wrote:  Nice detective work Angel!
Indeed!

(04-10-2021 08:03 PM)rprosperi Wrote:  Was this fact, that adjacent Pages in a given Port both bank-switch together well-known or is this a new discovery? And of course by 'well-known' I mean by you gurus, not the rest of us heathens....
I had forgotten it, but yes it was very well explained in the ZEPROM Module - Programmer's Manual, 1988, Pages 5 to 9

edit: also explained in the CMT-110/CMT-10 Owner's Manual, but that module uses a different bank switching scheme than HP/Zengrange.
04-10-2021, 09:15 PM
Post: #30
 cdmackay Senior Member Posts: 634 Joined: Sep 2018
RE: [41CL WARP] XEQ+ oddness
thanks Bob,

(04-10-2021 08:03 PM)rprosperi Wrote:  I believe (Angel, please correct me if I'm wrong) this doesn't occur on the 41X because the adjacent Pages in a common Port are not physically connected so the bank switch for one does not affect the other (one advantage of s/w based emulation )

unless some code somewhere assumes the hardware-based behaviour

that's good to know, thanks Bob.

Cambridge, UK
41CL/DM41X 12/15C/16C DM15/16 71B 17B/BII/bII+ 28S 42S/DM42 32SII 48GX 50g 35s 30b/WP34S Prime G2
& Casios, Rockwell 18R :)
04-10-2021, 09:16 PM
Post: #31
 cdmackay Senior Member Posts: 634 Joined: Sep 2018
RE: [41CL WARP] XEQ+ oddness
thanks Sylvain,

(04-10-2021 08:39 PM)Sylvain Cote Wrote:  I had forgotten it, but yes it was very well explained in the ZEPROM Module - Programmer's Manual, 1988, Pages 5 to 9

the discussion there of the 12K HP modules seems to suggest that it is OK to have both a single-page bank-switched module, along with a single-page non-banked module, in the same port?

Cambridge, UK
41CL/DM41X 12/15C/16C DM15/16 71B 17B/BII/bII+ 28S 42S/DM42 32SII 48GX 50g 35s 30b/WP34S Prime G2
& Casios, Rockwell 18R :)
04-11-2021, 07:04 AM (This post was last modified: 04-12-2021 06:27 AM by Ángel Martin.)
Post: #32
 Ángel Martin Senior Member Posts: 1,263 Joined: Dec 2013
RE: [41CL WARP] XEQ+ oddness
(04-10-2021 09:16 PM)cdmackay Wrote:  thanks Sylvain,

(04-10-2021 08:39 PM)Sylvain Cote Wrote:  I had forgotten it, but yes it was very well explained in the ZEPROM Module - Programmer's Manual, 1988, Pages 5 to 9

the discussion there of the 12K HP modules seems to suggest that it is OK to have both a single-page bank-switched module, along with a single-page non-banked module, in the same port?

Yeah, that's ok. There's no need to leave the other page blank: the port can be fully used as long as there aren't two, single-page, bank-switched ROMS in it.

So the rule of thumb is that the only restriction is for two bank-switched ROMS belonging to different Modules to be in the same port, that's what should be avoided - As you observe, the case of two, single-paged, bank-switched modules is a particular instance of the general rule above.

In truth, even that isn't always going to be a problem, only when one of the ROMS is accessing contents from the other (like it occurs with the WARP reading the auxiliary FATs of the PWRX in a secondary bank). But this is a bit too complex to use as a rule, so better stick to the first one.

I mentioned it before, this applies to the CL because it is the most flexible of all platforms. In the CL you can plug said configurations using the ROM images as you wish, for instance when you use the RAM or Flash locations you can plug the module pages straddling two ports.

Note that when using the IMDB mnemonic this issue is *sometimes* avoided based on the module size - but you're not completely protected either. Say for instance that you want to plug the HP-41 Advantage (41AD). If you choose page B that's also a port-straddling configuration and you're already pushing your luck a little, so rather don't!

This has nothing to do with being hardware-based or software-based emulation. In the DM41X case, it all depends on the MOD files settings. It's therefore also possible to run into this issue if the MOD file for a single-page ROM allows plugging it into the higher page within the port - and thus opening the possibility that the lower page of said port is used by another bank-switched module. This is BTW the preferred MOD setting, or otherwise you'll have blank holes in the I/O bus, as it occurs in the real machine when you plug two 4k-Modules in contiguous ports.

Finally, for the real HP-41 the bank-switching method is not implemented in the OS but in the module itself; so it is performed by the Advantage/HEPAX/ZEPROM chips when they "see" the proper instructions. This is mimicked by the CL at the ROM level and by the 41X at the MOD level (using the MOD file configuration), so it's obviously not performed by the plugged module since there isn't any.

PS.- A final comment about the locations used to plug certain modules: (not related to bank-switching). Remember that the YFNX must be plugged at a higher page number than the OS/X (or CCD-like ) for the extended catalogs to work. This is due to athe way the YFNX processes the I/O interrupt, masking it from the following ROMS in the bus.
04-11-2021, 07:25 AM (This post was last modified: 04-11-2021 07:26 AM by Ángel Martin.)
Post: #33
 Ángel Martin Senior Member Posts: 1,263 Joined: Dec 2013
RE: [41CL WARP] XEQ+ oddness
(04-10-2021 08:39 PM)Sylvain Cote Wrote:
(04-10-2021 08:03 PM)rprosperi Wrote:  Nice detective work Angel!
Indeed!

(04-10-2021 08:03 PM)rprosperi Wrote:  Was this fact, that adjacent Pages in a given Port both bank-switch together well-known or is this a new discovery? And of course by 'well-known' I mean by you gurus, not the rest of us heathens....
I had forgotten it, but yes it was very well explained in the ZEPROM Module - Programmer's Manual, 1988, Pages 5 to 9

edit: also explained in the CMT-110/CMT-10 Owner's Manual, but that module uses a different bank switching scheme than HP/Zengrange.

It's probably worth adding a note in the WARP manual. WARP is by far the one with the highest exposure to this, since it triggers the bank-switching of all other modules in the bus (something that was believed impossible previously BTW).
04-11-2021, 12:05 PM
Post: #34
 MeindertKuipers Member Posts: 144 Joined: Dec 2013
RE: [41CL WARP] XEQ+ oddness
This bank switching is still pretty complicated. Based on the documentation:
- HP41CL switches a bank per PORT (2 pages)
- MLDL2000 switches a bank per PORT (2 pages)
- Clonix/NoVRAM: probably switches per page, but I have not seen any real confirmation in the docs
- DM41X: appears to switch per page as per the .MOD settings
- real HP41: depends on the implementation in the module

In addition in the DM41X it is not possible to have bank switching in RAM pages, but this is very well possible in the 41CL and MLDL2000. Not certain for Clonix/NovRAM

Regards, Meindert
04-11-2021, 12:12 PM (This post was last modified: 04-12-2021 06:31 AM by Ángel Martin.)
Post: #35
 Ángel Martin Senior Member Posts: 1,263 Joined: Dec 2013
RE: [41CL WARP] XEQ+ oddness
(04-11-2021 12:05 PM)MeindertKuipers Wrote:  This bank switching is still pretty complicated. Based on the documentation:
- HP41CL switches a bank per PORT (2 pages)
- MLDL2000 switches a bank per PORT (2 pages)
- Clonix/NoVRAM: probably switches per page, but I have not seen any real confirmation in the docs
- DM41X: appears to switch per page as per the .MOD settings
- real HP41: depends on the implementation in the module

In addition in the DM41X it is not possible to have bank switching in RAM pages, but this is very well possible in the 41CL and MLDL2000. Not certain for Clonix/NovRAM

1. In the CL the internal pages (#4, #6, #7) do the bank-switching independently, single-page scheme.

2. I believe the Clonix/NoVo also follows the same scheme, single page if internal and port-based if external.

3. The DM41X definitely does whatever the MOD files specifies, which some times is not why you'd like to - like leaving blank pages in-between 4k modules.

4. V41 appears to be more intelligent in the module loading department, but I haven't really dug into it...
04-11-2021, 12:25 PM
Post: #36
 Sylvain Cote Senior Member Posts: 1,717 Joined: Dec 2013
RE: [41CL WARP] XEQ+ oddness
Thank you Ángel for this complete review of HP-41 bank switching.

(04-11-2021 12:05 PM)MeindertKuipers Wrote:  - Clonix/NoVRAM: probably switches per page, but I have not seen any real confirmation in the docs
Before 2020, bank switching was at the module level, to be more precise, all the pages of all the ROMs served by the modules switched at the same time.
Since 2020, bank switching is now done at page level. (not in the doc but in an email thread that I had with Diego in 2020)

(04-11-2021 12:05 PM)MeindertKuipers Wrote:  In addition in the DM41X it is not possible to have bank switching in RAM pages, but this is very well possible in the 41CL and MLDL2000. Not certain for Clonix/NovRAM
Bank switching is only supported for Flash pages not for RAM pages.
04-11-2021, 12:35 PM
Post: #37
 rprosperi Senior Member Posts: 5,069 Joined: Dec 2013
RE: [41CL WARP] XEQ+ oddness
@Angel - Thanks for the thorough and detailed explanation! These issues are obviously very subtle and the differing behavior from one platform to another makes it even more complex, all the more reason your explaining this here is important and will be helpful as a resource in the future.

Thanks!

--Bob Prosperi
04-11-2021, 02:12 PM (This post was last modified: 04-12-2021 02:31 AM by Sylvain Cote.)
Post: #38
 Sylvain Cote Senior Member Posts: 1,717 Joined: Dec 2013
RE: [41CL WARP] XEQ+ oddness
Incomplete list of HP & EPROM/Flash box/modules bank switched product introduction year ...
• 1983: HP-41CX released (page 5, BS)
• 1985: HP Advantage module released (12K ROM, BS)
• 1985: CMT-10-16KB module released (16K EPROM, BS)
• 1987: ZEPROM module released (16K EPROM, BS)
• 1987: HP IR Printer Module, with two banks always in page-6
• 1987: VM Electronics HEPAX Module, with FOUR banks in one self-relocating page
• 2003: Clonix-41 module released (24K Flash, BS) / latest: Clonix-D (48K Flash, BS)
• 2004: NoVRAM module released (24K Flash & 16K FRAM, BS) / latest: NoV-64d (48K Flash & 64K FRAM, BS)
• 2005: MLDL2000 card reader module released (255 ROM banks & 63 SRAM banks, BS)
• 2011: 41CL Beta boards shipped (2MB Flash & 512K SRAM, BS) / latest: 41CL v5 (8MB Flash & 512K SRAM, BS)
• 2020: DM41X released (6MB Flash, BS)
• 2020: bank switching emails exchanged with Monte, Diego, Meindert, Håkan, Ángel & Robert
CMT-10-16KB module from Corvallis MicroTechnology: (discontinued)
1. the module uses a 27C256 EPROM (256k bits = 16k of 16 bits words)
2. the module is split into four 4K blocks (0 to 3) of 16 bits words
3. extended 16 bits NUT instruction structure
1. bits 15 to 13 must be set to zero
2. bits 12 to 10 are for blocks switching
3. bits 9 to 0 are for NUT instructions
4. block switching is encoded in each 16 bits extended NUT instruction
1. bit 12 set to 1 indicate to the module internal firmware/hardware to interpret bits 11 and 10
2. bits 11 & 10 indicate the following: 00 = block 0, 01 = block 1, 10 = block 2, 11 = block 3
5. bank switching can also be done with modified ENBANK instructions
1. ENBANK1: 0x100 or 01 0000 0000 becomes 0001 0101 0000 0000 or 0x1500
2. ENBANK2: 0x180 or 01 1000 0000 becomes 0001 1001 1000 0000 or 0x1980
3. ENBANK3: 0x140 or 01 0100 0000 becomes 0001 1101 0100 0000 or 0x1D40 (not in the manual but can be extrapolated)
4. ENBANK4: 0x1C0 or 01 1100 0000 (not in the manual and not supported)
6. bank 1 even/lower page always contains 4K block 0
7. bank 1 odd/higher page often contains 4K block 1 (at boot up, mode changes, etc)
8. bank 1 odd/higher page is changed to the specified block (0 to 3) when the module encounters an instruction with block switching bits set
9. bank 1 odd/higher page is changed to the specified block (1 to 3) when a modified ENBANK1 to ENBANK3 instruction is interpreted

ZEPROM module from Zengrange: (discontinued)
1. ENBANK1 and ENBANK2 are supported(0x100, 0x180), ENBANK3 to ENBANK4 are not supported (0x140, 0x1C0)
1. ENBANK1 activate the first 8K (even/odd pages)
2. ENBANK2 activate the second 8K (even/odd pages)
2. to convert a 16KB flat module to a bank switched one, they first link the even/odd pages and then remap the second 8K to bank 2.

MLDL2000 card reader module (firmware v1.51+) from Meindert Kuipers: (discontinued)
1. support bank switching for all pages (0x0 to 0xF)
2. even/odd pages are linked (0x4/0x5, 0x6/0x7, 0x8/0x9, 0xA/0xB, 0xC/0xD, 0xE/0xF)
3. ENBANK1 to ENBANK4 are supported (0x100, 0x180, 0x140, 0x1C0)

Clonix & NoV modules from Diego Díaz:
1. ENBANK1 to ENBANK4 are supported (0x100, 0x180, 0x140, 0x1C0) for Flash based pages only (NoV RAM pages does not support BS)
2. support bank switching for pages 0x4 to 0xF
3. before 2020: bank switching is done at module level (all the pages of all the ROMs served by the module are switched at the same time)
4. since 2020: bank switching is done at page level

41CL boards from Monte Dalrymple:
1. ENBANK1 to ENBANK4 are supported (aka ENROMx, 0x100, 0x180, 0x140, 0x1C0)
2. page & bank mapping are done with the WCMD NEWT instruction and with the MMU (0x804xxx adresses)
3. extended 16 bits NUT instruction structure
1. bits 15 to 14 unused (ignored)
2. bits 13 to 12 used for turbo handling (bits = this/next instruction)
• 00 = turbo execute / turbo fetch (if enabled)
• 01 = normal execute / normal fetch
• 1x = refetch, normal execute / normal fetch
3. bits 11 to 10 unused (ignored)
4. bits 9 to 0 are for NUT instructions
4. pages that are bank switch enabled
1. even/odd port pages are linked (0x8/0x9, 0xA/0xB, 0xC/0xD, 0xE/0xF)
2. some lower pages are standalone (0x4, 0x6, 0x7)
3. some lower pages are linked (0x3/0x5)
The 0x3/0x5 linking is required by the CX Extended Functions.
The bank is switched by code in page 3 before a jump to code in page 5.
5. OS pages are not bank switch enabled (0x0, 0x1, 0x2)

DM41X from SwissMicros:
1. ENBANK1 to ENBANK4 are supported (0x100, 0x180, 0x140, 0x1C0)
2. support bank switching for pages 0x4 to 0xF
3. OS pages are not bank switch enabled (0x0, 0x1, 0x2, 0x3)
4. MOD file control module page switch definition

edit 1: typos
edit 3: added missing items from Ángel
edit 4: added 41CL correction from Monte
04-11-2021, 02:54 PM (This post was last modified: 04-11-2021 02:56 PM by Ángel Martin.)
Post: #39
 Ángel Martin Senior Member Posts: 1,263 Joined: Dec 2013
RE: [41CL WARP] XEQ+ oddness
(04-11-2021 02:12 PM)Sylvain Cote Wrote:  Incomplete list of HP & EPROM/Flash box/modules bank switched product introduction year ...
[list]
[*]1983: HP-41CX released (page 5, BS)
[*]1985: HP Advantage module released (12K ROM, BS)

......

[*] HP also introduced the IR Printer Module circa 1987, with two banks always in page-6.
[*] VM Electronics Introduced the HEPAX Module in 1987 with FOUR banks in one self-relocating page.
04-11-2021, 05:45 PM
Post: #40
 MeindertKuipers Member Posts: 144 Joined: Dec 2013
RE: [41CL WARP] XEQ+ oddness
(04-11-2021 02:12 PM)Sylvain Cote Wrote:  Incomplete list of HP & EPROM/Flash box/modules bank switched product introduction year ...
...

Very impressive this list, thanks Sylvain! Maybe store this in the articles section?

Regards, Meindert
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