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(SOLVED) 41CL - DOUBLE HEPAX ACCESS and MMU CONFIG
08-13-2019, 03:54 PM (This post was last modified: 08-22-2019 10:45 AM by Podalirius.)
Post: #1
(SOLVED) 41CL - DOUBLE HEPAX ACCESS and MMU CONFIG
Hi! I have the need to access to my HEPAX installation
in MMU 0 or another MMU. It is possible?
Before to obtain a MEMORY LOST, I need your help!
My 41CL is full updated and I typed XEQ CFGINI.
Now I trying to modify some page to custom for my
necessity.
Any suggestions will be very appreciated!!!
Thank you very much!!!
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08-14-2019, 12:13 AM
Post: #2
RE: 41CL - DOUBLE HEPAX ACCESS
(08-13-2019 03:54 PM)Podalirius Wrote:  Hi! I have the need to access to my HEPAX installation in MMU 0 or another MMU. It is possible?
I see no reason why not, so I would assume yes it is possible.

(08-13-2019 03:54 PM)Podalirius Wrote:  My 41CL is full updated and I typed XEQ CFGINI.
From which module ?

(08-13-2019 03:54 PM)Podalirius Wrote:  Now I trying to modify some page to custom for my necessity.
What is your current configuration ?
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08-14-2019, 06:00 AM (This post was last modified: 08-14-2019 06:14 AM by Podalirius.)
Post: #3
RE: 41CL - DOUBLE HEPAX ACCESS
(08-14-2019 12:13 AM)Sylvain Cote Wrote:  
(08-13-2019 03:54 PM)Podalirius Wrote:  Hi! I have the need to access to my HEPAX installation in MMU 0 or another MMU. It is possible?
I see no reason why not, so I would assume yes it is possible.

(08-13-2019 03:54 PM)Podalirius Wrote:  My 41CL is full updated and I typed XEQ CFGINI.
From which module ?

(08-13-2019 03:54 PM)Podalirius Wrote:  Now I trying to modify some page to custom for my necessity.
What is your current configuration ?

Hi, Thank you very much for help!
I updated my 41CL with rom_files_190731.zip.
In this, MMU has 16 different configs fro 0 (Primary) to F and
Mr. Monte created a new instruction CFGINI, in the module YFNF
that install by itself twelve configurations from MMU 4 to MMU F.
I modified a copy of MMU 4, stored in MMU 0 as Primary, as this:
MMU 4, alias 9PWR
PORT__ORIGINAL IN MMU 4___________MY IN MMU 0
4..........4LIB.............................................4LIB
5
6..........OSX3...........................................OSX3
7..........YFNX...........................................YFNX
8..........PWRX..........................................PWRX
9..........WARP...........................................WARP
A..........XPMM.........................................XPMM
B..........4TBX...........................................HEP2
C..........ROMX..........................................HEPAX RAM 1
D..........HEP2...........................................HEPAX RAM 2
E..............................................................HEPAX RAM 3
F..............................................................HEPAX RAM 4

HEPAX RAM 1-4 created with:
XEQ HEP16 Y C
HEP16 output:
0B9>808
0B9>809
0B9>80A
0B9>80B
H:DIR EMPTY REGISTER X = 651

XEQ HEPINI 4 C

XEQ HEPROOM output is 2610

I have the need to change also MMU F, alias 9HIL, by Mr. Monte devoted to HP-IL operations
as:
PORT____________MODULE
4.............................4LIB
5
6.............................HILN (HP-IL Printer)
7.............................HILM (HP-IL)
8.............................OSX3
9.............................YFNX
A............................. X MASS (HP-IL MASS STORAGE)
B.............................HEP2
C.............................HEPAX RAM 1
D.............................HEPAX RAM 2
E.............................HEPAX RAM 3
F.............................HEPAX RAM 4

I connect my 41CL via HP-IL to a pyILBOX.

Again, Thank you for help!
With best regards.
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08-15-2019, 05:36 AM (This post was last modified: 08-15-2019 02:12 PM by Sylvain Cote.)
Post: #4
RE: 41CL - DOUBLE HEPAX ACCESS
Before going into Podalirius specific request and in order to understand what is going on, I will do some 41CL MMU space exploration

References:
  • Manual.: 41CL User Manual (sy41cl.pdf, YFNZ & YFNP)
    Chapter: Memory Management (P.62) / Fncs: MMUEN, MMUDIS, YRES, PLUGH, PLUG1L
    .
  • Manual.: 41CL Extreme Functions (cl_extreme.pdf, YFNX)
    Chapter: MMU Functions (P.8) / Fncs: MMUCLP, MMUCLS
    .
  • Manual.: 41CL Memory Functions (cl_memory.pdf, YFNF)
    Chapter: Address Pointer Functions (P.6) / Fncs: STOXP
    Chapter: General Memory Functions (P.12) / Fncs: YPEEK+
    Chapter: Configuration Functions (P.32) / Fncs: CFGINI
    .
  • Manual.: 41CL Memory Reference (mem_ref.pdf)
    Chapter: RAM Memory Details (P.28 @ P.31)

First, we need to do the basic setup
Code:
MMUDIS              // disable MMU
MMUCLR              // clear MMU configuration
"YFNX"
PLUGH               // plug 41CL Extreme Functions into port 7
"YFNF"
PLUG1L              // plug 41CL Memory  Functions into port 8
TURBO50             // fast mode
MMUEN               // enable MMU

Before doing the exploration, we need to do some cleanup ...
Code:
MMUCLS              // Clear Secondary MMU Registers (0x804100..0x8043FF)
MMUCLP              // Clear Primary   MMU Registers (0x804000..0x8040FF)
CAT 2               // Oups we lost our current MMU mapping
YRES                // Recovery, same as MMUDIS, part of "-CL TIME" module

Well, we need to redo the basic setup but skip the cleaning part, already done
Code:
"YFNX"
PLUGH               // plug 41CL Extreme Functions into port 7
"YFNF"
PLUG1L              // plug 41CL Memory  Functions into port 8
MMUEN               // enable MMU

To speedup things we will assign some functions to the user keys
Code:
ASN "STOXP"  15     // assign STOXP  to LN  key
ASN "YPEEK+" 25     // assign YPEEK+ to TAN key
USER                // activate USER mode

First question: where is the YFNX and YFNF mapping stored ?

Lets do some basic exploration in MMU space
Code:
"804060"
STOPXP (LN  key)    // store memory address where we start looking into the primary MMU registers.
Code:
YPEEK+ (TAN key)    // 806060-0000 : Page 6 : Bank 1 : Set 0 : disabled : unlocked : no-multi : no-mapping
YPEEK+ (TAN key)    // 806061-0000 : Page 6 : Bank 1 : Set 1 : disabled : unlocked : no-multi : no-mapping
YPEEK+ (TAN key)    // 806062-0000 : Page 6 : Bank 1 : Set 2 : disabled : unlocked : no-multi : no-mapping
YPEEK+ (TAN key)    // 806063-0000 : Page 6 : Bank 1 : Set 3 : disabled : unlocked : no-multi : no-mapping
Code:
YPEEK+ (TAN key)    // 806064-0000 : Page 6 : Bank 3 : Set 0 : disabled : unlocked : no-multi : no-mapping
YPEEK+ (TAN key)    // 806065-0000 : Page 6 : Bank 3 : Set 1 : disabled : unlocked : no-multi : no-mapping
YPEEK+ (TAN key)    // 806066-0000 : Page 6 : Bank 3 : Set 2 : disabled : unlocked : no-multi : no-mapping
YPEEK+ (TAN key)    // 806067-0000 : Page 6 : Bank 3 : Set 3 : disabled : unlocked : no-multi : no-mapping
Code:
YPEEK+ (TAN key)    // 806068-0000 : Page 6 : Bank 2 : Set 0 : disabled : unlocked : no-multi : no-mapping
YPEEK+ (TAN key)    // 806069-0000 : Page 6 : Bank 2 : Set 1 : disabled : unlocked : no-multi : no-mapping
YPEEK+ (TAN key)    // 80606A-0000 : Page 6 : Bank 2 : Set 2 : disabled : unlocked : no-multi : no-mapping
YPEEK+ (TAN key)    // 80606B-0000 : Page 6 : Bank 2 : Set 3 : disabled : unlocked : no-multi : no-mapping
Code:
YPEEK+ (TAN key)    // 80606C-0000 : Page 6 : Bank 4 : Set 0 : disabled : unlocked : no-multi : no-mapping
YPEEK+ (TAN key)    // 80606D-0000 : Page 6 : Bank 4 : Set 1 : disabled : unlocked : no-multi : no-mapping
YPEEK+ (TAN key)    // 80606E-0000 : Page 6 : Bank 4 : Set 2 : disabled : unlocked : no-multi : no-mapping
YPEEK+ (TAN key)    // 80606F-0000 : Page 6 : Bank 4 : Set 3 : disabled : unlocked : no-multi : no-mapping
Code:
YPEEK+ (TAN key)    // 806070-800A : Page 7 : Bank 1 : Set 0 : enabled  : unlocked : no-multi : mapped to 0x00A YFNX
YPEEK+ (TAN key)    // 806071-0000 : Page 7 : Bank 1 : Set 1 : disabled : unlocked : no-multi : no-mapping
YPEEK+ (TAN key)    // 806072-0000 : Page 7 : Bank 1 : Set 2 : disabled : unlocked : no-multi : no-mapping
YPEEK+ (TAN key)    // 806073-0000 : Page 7 : Bank 1 : Set 3 : disabled : unlocked : no-multi : no-mapping
Code:
YPEEK+ (TAN key)    // 806074-800A : Page 7 : Bank 3 : Set 0 : enabled  : unlocked : no-multi : mapped to 0x00A YFNX
YPEEK+ (TAN key)    // 806075-0000 : Page 7 : Bank 3 : Set 1 : disabled : unlocked : no-multi : no-mapping
YPEEK+ (TAN key)    // 806076-0000 : Page 7 : Bank 3 : Set 2 : disabled : unlocked : no-multi : no-mapping
YPEEK+ (TAN key)    // 806077-0000 : Page 7 : Bank 3 : Set 3 : disabled : unlocked : no-multi : no-mapping
Code:
YPEEK+ (TAN key)    // 806078-800A : Page 7 : Bank 2 : Set 0 : enabled  : unlocked : no-multi : mapped to 0x00A YFNX
YPEEK+ (TAN key)    // 806079-0000 : Page 7 : Bank 2 : Set 1 : disabled : unlocked : no-multi : no-mapping
YPEEK+ (TAN key)    // 80607A-0000 : Page 7 : Bank 2 : Set 2 : disabled : unlocked : no-multi : no-mapping
YPEEK+ (TAN key)    // 80607B-0000 : Page 7 : Bank 2 : Set 3 : disabled : unlocked : no-multi : no-mapping
Code:
YPEEK+ (TAN key)    // 80607C-800A : Page 7 : Bank 4 : Set 0 : enabled  : unlocked : no-multi : mapped to 0x00A YFNX
YPEEK+ (TAN key)    // 80607D-0000 : Page 7 : Bank 4 : Set 1 : disabled : unlocked : no-multi : no-mapping
YPEEK+ (TAN key)    // 80607E-0000 : Page 7 : Bank 4 : Set 2 : disabled : unlocked : no-multi : no-mapping
YPEEK+ (TAN key)    // 80607F-0000 : Page 7 : Bank 4 : Set 3 : disabled : unlocked : no-multi : no-mapping
Code:
YPEEK+ (TAN key)    // 806080-8167 : Page 7 : Bank 1 : Set 0 : enabled  : unlocked : no-multi : mapped to 0x167 YFNF
YPEEK+ (TAN key)    // 806081-0000 : Page 7 : Bank 1 : Set 1 : disabled : unlocked : no-multi : no-mapping
YPEEK+ (TAN key)    // 806082-0000 : Page 7 : Bank 1 : Set 2 : disabled : unlocked : no-multi : no-mapping
YPEEK+ (TAN key)    // 806083-0000 : Page 7 : Bank 1 : Set 3 : disabled : unlocked : no-multi : no-mapping
Code:
YPEEK+ (TAN key)    // 806084-8167 : Page 7 : Bank 3 : Set 0 : enabled  : unlocked : no-multi : mapped to 0x167 YFNF
YPEEK+ (TAN key)    // 806085-0000 : Page 7 : Bank 3 : Set 1 : disabled : unlocked : no-multi : no-mapping
YPEEK+ (TAN key)    // 806086-0000 : Page 7 : Bank 3 : Set 2 : disabled : unlocked : no-multi : no-mapping
YPEEK+ (TAN key)    // 806087-0000 : Page 7 : Bank 3 : Set 3 : disabled : unlocked : no-multi : no-mapping
Code:
YPEEK+ (TAN key)    // 806088-8167 : Page 7 : Bank 2 : Set 0 : enabled  : unlocked : no-multi : mapped to 0x167 YFNF
YPEEK+ (TAN key)    // 806089-0000 : Page 7 : Bank 2 : Set 1 : disabled : unlocked : no-multi : no-mapping
YPEEK+ (TAN key)    // 80608A-0000 : Page 7 : Bank 2 : Set 2 : disabled : unlocked : no-multi : no-mapping
YPEEK+ (TAN key)    // 80608B-0000 : Page 7 : Bank 2 : Set 3 : disabled : unlocked : no-multi : no-mapping
Code:
YPEEK+ (TAN key)    // 80608C-8167 : Page 7 : Bank 4 : Set 0 : enabled  : unlocked : no-multi : mapped to 0x167 YFNF
YPEEK+ (TAN key)    // 80608D-0000 : Page 7 : Bank 4 : Set 1 : disabled : unlocked : no-multi : no-mapping
YPEEK+ (TAN key)    // 80608E-0000 : Page 7 : Bank 4 : Set 2 : disabled : unlocked : no-multi : no-mapping
YPEEK+ (TAN key)    // 80608F-0000 : Page 7 : Bank 4 : Set 3 : disabled : unlocked : no-multi : no-mapping
Code:
we stop here for now because everything else is set to 0000

From the above trace, we have found where PLUGH and PLUG1L put its mapping information, meaning SET 0 which is the default environment and in all banks of the specific page.

Second question: what does the CFGINI do ?

From Monte manual: Executing CFGINI (Initialize Alternate Configurations) loads twelve of the alternate configurations ...

ok, but where can I see this for myself !!!

Previously we have cleaned that memory space with MMUCLS, so we should see only 0000 everywhere, let's see
Code:
"804140"
STOPXP (LN  key)    // store memory address of page 4 of the secondary MMU registers, set 4 to 7.
Code:
YPEEK+ (TAN key)    // 806140-0000 : Page 4 : Bank 1 : Set 4 : disabled : unlocked : no-multi : no-mapping
YPEEK+ (TAN key)    // 806141-0000 : Page 4 : Bank 1 : Set 5 : disabled : unlocked : no-multi : no-mapping
YPEEK+ (TAN key)    // 806142-0000 : Page 4 : Bank 1 : Set 6 : disabled : unlocked : no-multi : no-mapping
YPEEK+ (TAN key)    // 806143-0000 : Page 4 : Bank 1 : Set 7 : disabled : unlocked : no-multi : no-mapping
Code:
"804190"
STOPXP (LN  key)    // store memory address of page 9 of the secondary MMU registers, set 4 to 7.
Code:
YPEEK+ (TAN key)    // 806190-0000 : Page 9 : Bank 1 : Set 4 : disabled : unlocked : no-multi : no-mapping
YPEEK+ (TAN key)    // 806191-0000 : Page 9 : Bank 1 : Set 5 : disabled : unlocked : no-multi : no-mapping
YPEEK+ (TAN key)    // 806192-0000 : Page 9 : Bank 1 : Set 6 : disabled : unlocked : no-multi : no-mapping
YPEEK+ (TAN key)    // 806193-0000 : Page 9 : Bank 1 : Set 7 : disabled : unlocked : no-multi : no-mapping
... at that point we have confirmed that everything is set to zero.

Lets load the configuration tables from ROM with CFGINI
Code:
CFGINI              // load configuration table from ROM to RAM

Lets do some validation, you need to validate this with cl_memory.pdf page 32
Code:
"804140"
STOPXP (LN  key)    // store memory address of page 4 of the secondary MMU registers, set 4 to 7.
Code:
YPEEK+ (TAN key)    // 806140-8120 : Page 4 : Bank 1 : Set 4 : enabled  : unlocked : no-multi : mapped to 0x120 4LIB config 9PWR
YPEEK+ (TAN key)    // 806141-8120 : Page 4 : Bank 1 : Set 5 : enabled  : unlocked : no-multi : mapped to 0x120 4LIB config 9MTH
YPEEK+ (TAN key)    // 806142-8120 : Page 4 : Bank 1 : Set 6 : enabled  : unlocked : no-multi : mapped to 0x120 4LIB config 9SCI
YPEEK+ (TAN key)    // 806143-8120 : Page 4 : Bank 1 : Set 7 : enabled  : unlocked : no-multi : mapped to 0x120 4LIB config 9INF
Code:
"804190"
STOPXP (LN  key)    // store memory address of page 9 of the secondary MMU registers, set 4 to 7.
Code:
YPEEK+ (TAN key)    // 806190-81B8 : Page 9 : Bank 1 : Set 4 : enabled  : unlocked : no-multi : mapped to 0x1B8 WARP config 9PWR (WARP:WARPB1)
YPEEK+ (TAN key)    // 806191-A1A4 : Page 9 : Bank 1 : Set 5 : enabled  : unlocked : multi-lp : mapped to 0x1A4 SM44 config 9MTH (SM44:HLMAT41) (multi last page)
YPEEK+ (TAN key)    // 806192-80D6 : Page 9 : Bank 1 : Set 6 : enabled  : unlocked : no-multi : mapped to 0x0D6 ISOL config 9SCI
YPEEK+ (TAN key)    // 806193-81DB : Page 9 : Bank 1 : Set 7 : enabled  : unlocked : no-multi : mapped to 0x1DB CRTO config 9INF
... at that point we have confirmed that the secondary MMU registers does contains the table data described in the cl_memory.pdf document page 32.

It is 01h30 here, I am going to bed, follow-up tomorrow ...

edit: typo
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08-15-2019, 08:00 PM
Post: #5
RE: 41CL - DOUBLE HEPAX ACCESS
A slightly simpler way to see what the CFGINI function loads into the MMU registers is to look at the source code for the YFNF module. Specifically, the table starting at 0xB70.

There are two source files, because each table entry contains 16 bits, but the V41 assembler only understands 10 bit instructions. I merge the two resulting .ROM files to create the actual .ROM file that is loaded in Flash. The two source files are available on the 41CL website on the "software" page.

Monte
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08-17-2019, 02:15 PM
Post: #6
RE: 41CL - DOUBLE HEPAX ACCESS
(08-15-2019 08:00 PM)Monte Dalrymple Wrote:  A slightly simpler way to see what the CFGINI function loads into the MMU registers is to look at the source
code for the YFNF module. Specifically, the table starting at 0xB70.
Actually, I did read the source code to confirm my finding. Very well documented code btw.
My goal here was to do it like a normal user by understanding the feature from the documentation and behaviour.
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08-17-2019, 02:17 PM
Post: #7
RE: 41CL - DOUBLE HEPAX ACCESS
Sorry Podalirius for the time it takes to get your answers, I had to work on my home and also needed to experiment a little before coming up with the solution.
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08-17-2019, 02:22 PM (This post was last modified: 08-17-2019 02:46 PM by Sylvain Cote.)
Post: #8
RE: 41CL - DOUBLE HEPAX ACCESS
Hello Monte,

When playing with CFGINI and with 9??? configuration with PLUG/PPLUG, I came up with some duplicate XROM issues.
In order to solve them I manually resolved all the modules XROM used in the configuration table and here is the result.

Sylvain

The following table was taken from Monte 41CL Memory Functions document and I have added XROM numbers to it.
Code:
Set  >    4         5         6         7         8         9         A         B         C         D         E         F   
PLUG > 9PWR:XR   9MTH:XR   9SCI:XR   9INF:XR   9PRG:XR   9ELE:XR   9MEC:XR   9MAP:XR   9PLY:XR   9BGM:XR   9CST:XR   9HIL:XR
Page   -------   -------   -------   -------   -------   -------   -------   -------   -------   -------   -------   -------
Code:
   4   4LIB:--   4LIB:--   4LIB:--   4LIB:--   4LIB:--   4LIB:--   4LIB:--   4LIB:--   4LIB:--   4LIB:--   4LIB:--   4LIB:--
   5                                                                                                                        
   6   OSX3:05   OSX3:05   OSX3:05   OSX3:05             OSX3:05   OSX3:05   OSX3:05   OSX3:05   OSX3:05                    
   7   YFNX:15   YFNX:15   YFNX:15   YFNX:15   YFNX:15   YFNX:15   YFNX:15   YFNX:15   YFNX:15   YFNX:15   YFNX:15          
   8   PWRX:12   SM44:03   PWRX:12   16CS:16   YUPS:31   ETS5:10   ETS3:12   METX:30   FUNS:10   CHES:08   YUPS:31   OSX3:05
   9   WARP:21   SM44:02   ISOL:11   CRTO:10   16CS:16   ETS5:20   ETS3:--   5MAD:--   FUNS:--   CHES:--   YFNF:16   DEV2:22
Code:
   A   XPMM:20   4MTI:22   NONL:17   RCSN:09             EEFD:17   ETS4:08   WORD:31   FUNS:--   PPOK:10             DEV2:24
   B   4TBX:13   4MTI:24   XTAT:06   PWRX:12             EEFD:18   ETS4:14   WORD:--   FUNS:--   MAZZ:16             EXTI:27
   C   ROMX:31   Z4DL:01   CURV:04   BASI:08             UNIT:10   UNIT:10   CITY:30   RUBK:08   RGME:18             EXIO:23
   D   HEP2:07   Z4DL:01   CURV:--   BASI:11             CIRC:06   MCHN:12   CLND:12   4WIN:16   RGME:--             YFNX:15
   E             SERI:18   EPTC:17   FRML:30             EENG:15   MENG:16   SUD1:16   AGAM:30   GSWP:09             DACQ:21
   F             ADVG:12   ELIX:16   FRMX:31             ETS9:16   NBOD:06   CRTO:10   AGAM:--   GSWP:--             DACQ:31

Notes:
  1. An XR of -- means there is not FAT for the ROM
  2. Error in document cl_memory.pdf (2018-12-26), page 32, configuration table: [PLUG: 9INF], [Page: F] should be FRMX and not FRML
  3. Error in document mem_xref.pdf (2019-07-31), page 12, CITY XROM should be 30 and not 18
  4. There are duplicate XROM in 9SCI => [XROM:17 > NONL & EPTC]
  5. There are duplicate XROM in 9ELE => [XROM:10 > ETS5 & UNIT] and [XROM:15 > YFNX & EENG]
  6. There are duplicate XROM in 9MEC => [XROM:12 > ETS3 & MCHN]
  7. There are duplicate XROM in 9MAP => [XROM:30 > METX & CITY]

edit: typo
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08-17-2019, 02:45 PM (This post was last modified: 08-17-2019 03:11 PM by Podalirius.)
Post: #9
RE: 41CL - DOUBLE HEPAX ACCESS
Hi, I very appreciate all your efforts!!!
I am not an assembler programmer,
however I am very interested to learn something more, as the 41CL manuals
are for me a bit difficult, so I ask Mr. Sylvain Cote
to continue with his explications on CFGINI and MMU(s) settings,
so useful and clear for me! (and maybe also for others)

My first question was on the possility to have two
HEPAX installations in two separate MMU,
also without use CFGINI, but I am very interested also
on CFGINI and MMU(s) settings, so I decided to wait for
all your explications to learn more, before try to configure
the MMU(s) with CFGINI.

On CFGINI use, I triyed working with the MMU(s) installed by CFGINI, in maybe every mode
but is impossible and also a powerful source of MEMORY LOST,
because with EXCFG and RCLCFG the modules are superimposed
in ports so is possible that more ports are linked to the same module.
Even if I use PPLUG to delete a module and insert the new correct module
the MEMORY LOST error is a possibility very real!

I hope in your help!
I thank you ALL so much!!!
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08-17-2019, 03:32 PM (This post was last modified: 08-17-2019 03:42 PM by Sylvain Cote.)
Post: #10
RE: 41CL - DOUBLE HEPAX ACCESS
(08-17-2019 02:45 PM)Podalirius Wrote:  Hi, I very appreciate all your efforts, but I am NOT an Assembler programmer!!!
I understand that and that is why I am taking this path.

(08-17-2019 02:45 PM)Podalirius Wrote:  If CFGINI is too complex for me, I can make a second MMU setting without it.
ok

(08-17-2019 02:45 PM)Podalirius Wrote:  My question is NOT on CFGINI and how it works, ...
What took me on the CFGINI part at first was your comment here:
(08-14-2019 06:00 AM)Podalirius Wrote:  I have the need to change also MMU F, alias 9HIL, by Mr. Monte devoted to HP-IL operations

I am an old 41CL user, so every time I need to swap a MMU configuration, I simply erase the MMU setting and manually redo the configuration so I had never used the MMU configurations functions (CFGINI, RCLCFG, STOCFG, etc) before and I had to learn it first.
This posts are simply a documented logs of my findings while learning, unfortunately I also found issues with the MMU configuration table content and I had to resolve those before going further.

(08-17-2019 02:45 PM)Podalirius Wrote:  I tryed working with the MMU(s) installed by CFGINI, in maybe every mode but is impossible and also a powerful source of MEMORY LOST,
because with EXCFG and RCLCFG the modules are superimposed in ports so is possible that more ports are linked to the same module.
Even if I use PPLUG to delete a module and insert the new correct module the MEMORY LOST error is a possibility very real!
Its not impossible, you just need to understand how it is working and that takes time and patience.

(08-17-2019 02:45 PM)Podalirius Wrote:  .. but simply if is possible or not to have 2 HEPAX installations.
Yes it is possible, but you must understand that the HePaX modules used all the tricks in the books to give you more RAM and some special attention must be made to correctly backup or restore RAM content.
The 41CL is also a big beast to master and making both play well together is not a simple matter, at least for me.

To backup and restore multiple HePaX setup in the 41CL, there are two things you must take into account: the MMU configuration Set 0 and the HePaX RAM pages.
Because on how HePaX works, it is not enough to save the MMU configuration Set 0 you also have to save the pages where are located the HePaX RAM or else you will loose your HePaX RAM data.
Here RCLCFG and STOCFG will not be of any help, we need to find a way to backup the MMU configuration Set 0 and the HePaX RAM to either, another RAM block or offline to a LIF file.
I will focus on that part and continue with my rambling with the MMU configuration after.

Quote:I hope in your help!
Same here Wink

Sylvain

edit: typo
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08-17-2019, 05:28 PM
Post: #11
RE: 41CL - DOUBLE HEPAX ACCESS
(08-17-2019 02:45 PM)Podalirius Wrote:  On CFGINI use, I triyed working with the MMU(s) installed by CFGINI, in maybe every mode
but is impossible and also a powerful source of MEMORY LOST,
because with EXCFG and RCLCFG the modules are superimposed
in ports so is possible that more ports are linked to the same module.
Even if I use PPLUG to delete a module and insert the new correct module
the MEMORY LOST error is a possibility very real!

Can you give some examples of how you obtained MEMORY LOST when working with the MMU? I tried to reduce the possibility of MEMORY LOST errors, so if there are things I missed I would like to know.

If you are using YFNX any port that has a physical module plugged in is supposed to be automatically marked as "LOCKED" so that you can't accidentally create a conflict. And the OS should properly handle the case where two identical images are plugged in to different ports via the MMU.

As far as the HEPAX RAM, as far as the 41CL knows it's just another chunk of memory selected via the MMU. If you want to keep the HEPAX RAM the same across configurations, just mark those pages as "locked" and the hardware will protect them. If you swap out different copies of HEPAX RAM via the MMU, all of the contents of the HEPAX RAM are still there in 41CL RAM, untouched unless you deliberately do something to them. Unless I misunderstand how the HEPAX chaining works (it's all contained within the 4k page) all of the relevant page chaining information is also preserved.

Monte
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08-17-2019, 05:33 PM
Post: #12
RE: 41CL - DOUBLE HEPAX ACCESS
(08-17-2019 02:22 PM)Sylvain Cote Wrote:  Notes:
  1. An XR of -- means there is not FAT for the ROM
  2. Error in document cl_memory.pdf (2018-12-26), page 32, configuration table: [PLUG: 9INF], [Page: F] should be FRMX and not FRML
  3. Error in document mem_xref.pdf (2019-07-31), page 12, CITY XROM should be 30 and not 18
  4. There are duplicate XROM in 9SCI => [XROM:17 > NONL & EPTC]
  5. There are duplicate XROM in 9ELE => [XROM:10 > ETS5 & UNIT] and [XROM:15 > YFNX & EENG]
  6. There are duplicate XROM in 9MEC => [XROM:12 > ETS3 & MCHN]
  7. There are duplicate XROM in 9MAP => [XROM:30 > METX & CITY]

edit: typo

I could have sworn that I checked these when I got them from 'Angel, but apparently not. I'll have to figure out which ones to remove and release a new version of YFNF in the next Flash update.

I tried using CHKXROM in YFNX on one of these collisions and it didn't report a conflict like it's supposed to, so there if a bug somewhere in that function. Something else to look into.
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08-17-2019, 08:13 PM
Post: #13
RE: 41CL - DOUBLE HEPAX ACCESS
Hi, this is to reply to you Mr, Sylvain Cote and to Mr. Monte:

-To Mr. Sylvain Cote:
I don't know English so well to write a letter without the help of a dictionary,
so I need same time to write a message and post it here.
When I wrote my previous message your last messages (of you and of Mr. Monte)
are not present. Only then I confirmed my message I see and read your last messages!
I understood that installing the Hepax module on two MMU is a complex thing,
if is possible, because I don't know how to make the Hepax RAM pages accessible
also by another equal installation on another MMU.
I read very carefully your explications, because these are more similar to a book
on 41CL rather than 41CL manuals.
If installing Hepax on two MMU will be not possible, I will be happy again, because
of this things that you explain and teach me!

-To Mr. Monte
It is possible I am wrong: I thought that after XEQ CFGINI, with EXCFG I can swap
the MMU configurations without any problem.
Mr. Sylvain Cote teach me that this is not so easy.
I have a pyILBOX to connect the 41CL via HP-IL to some emulated periferals so I
use frequently the HP-IL. My first configs after CFGINI are readable In my second reply.
When I given the command EXCFG F the 41CL crashed, I extracted and reinserted
the batteries and obtained MEMORY LOST. Reading your instructions in 41CL Extreme Functions
and in 41CL Memory Functions, I see that the YFNX in port D on 9HIL was now present
also in the 9PWR installed by me in MMU 0 with RCLCFG 4.
Tha 41CL display DUP XROM 15, then, CONFIG BAD.
After many others attempts, with or without MEMORY LOST,
I thought to make this operations:
Procedure A - EXCHANGE MMU so that MMU 0 = 9PWR and MMU F = 9HIL
XEQ EXCFG F
XEQ MMUDIS
"EMPT 6" XEQ PPLUG to destroy PRINTER
"EMPT 7" XEQ PPLUG to destroy HP-IL
"PWRX" XEQ PLUG1L to overlap the OSX3 from 9HIL
"OSX3 6" XEQ PPLUG
"YFNX 7" XEQ PPLUG
XEQ MMUEN

Procedure B - EXCHANGE MMU so that MMU 0 = 9HIL and MMU F = 9PWR
XEQ EXCFG F
XEQ MMUDIS
"EMPT 6" XEQ PPLUG to destroy OSX3 from 9PWR to make space for PRINTER
"EMPT 7" XEQ PPLUG to destroy YFNX from 9PWR to make space for HP-IL
XEQ MMUEN

After installing 9PWR on MMU 0 with TCLCFG 4:
XEQ EXCFG F
Procedure B
OFF and ON
OK
To return at standard config MMU 0 = 9PWR and MMU F = 9HIL:
XEQ EXCFG F
Procedure A
OFF and ON
41CL crashed, than MEMORY LOST.
I hope this is of some utility for you,
but it is possible that all this is useless for you. I am not
an assembler programmer, and is possible that my tests are very
insufficient. This is actually the best of my knowledge.

I thank so much ALL of you!

P.S.: For me the 41CL, without the help in this Forum, is very similar to an iron!!!
It is for it that I greatly appreciate your work and help!!!
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08-18-2019, 08:52 PM (This post was last modified: 08-18-2019 08:54 PM by Monte Dalrymple.)
Post: #14
RE: 41CL - DOUBLE HEPAX ACCESS
As is mentioned in the manual, Configuration F requires more work to use because in CFG F the YFNX image is in a different page than all of the other configurations. This means that if you try to load this configuration directly, when the function terminates the code won't be there any more and you'll get a MEMORY LOST.

To switch to CFG F and HP-IL you will need to do the following:

MMUDIS (disable MMU and force the machine to use YFNZ in page 7)
XEQ MMUCLR (clear all of the previous configuration)
"YFNX" (select YFNX)
XEQ PLUG3U (plug YFNX into Port 3 upper half)
XEQ MMUEN (enable the MMU with YFNX in the location consistent with CFG F)
XEQ RCLCFG F (load CFG F)

Now you can turn off the machine and plug in the HP-IL module.


When you want to switch back to another configuration:

Turn off the machine and remove the HP-IL module.
Turn the machine back on.

MMUDIS (disable MMU and force the machine to use YFNZ in page 7)
XEQ MMUCLR (clear all of the previous configuration)
"YFNX" (select YFNX)
XEQ PLUGH (plug YFNX into Page 7 where the HP-IL module resided)
XEQ MMUEN (enable the MMU with YFNX in Page 7)
XEQ RCLCFG 0 (load CFG 0 or whatever other configuration you prefer)


I will be adding this information to the Extreme Functions manual. I originally left it as an exercise for the reader, which was clearly a mistake.

If there was room in the code it would obviously be better to recognize where YFNX was located and automatically handle all of this stuff. But I'm pretty sure that there aren't enough bytes left to do this.
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08-19-2019, 07:47 AM (This post was last modified: 08-19-2019 07:47 AM by Ángel Martin.)
Post: #15
RE: 41CL - DOUBLE HEPAX ACCESS
(08-17-2019 05:33 PM)Monte Dalrymple Wrote:  I tried using CHKXROM in YFNX on one of these collisions and it didn't report a conflict like it's supposed to, so there if a bug somewhere in that function. Something else to look into.

Pls. let me know which configuration is not properly trapped and I'll see to correct the problem. CHKSYS checks for conflicting XROM numbers that also have FAT functions, meaning that a second page with the same XROm id# but without functions is not considered to be a conflict. This situation is relatively frequent (AECROM, etc...).

ÁM
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08-19-2019, 11:05 AM
Post: #16
RE: 41CL - DOUBLE HEPAX ACCESS
Hi, to say thank you so much seem to me very little for
all this help!!!!!!
It remain the problem with the Hepax module:
Is possible to install it twice?
The motivation is that my old configuration
has two Hepax RAM pages (HPX8) and also the HP-IL.
Now, with the new MMU configurations created by
Mr. Monte, the HP-IL settings resides on 9HIL and
with no space for Hepax. I tried to modify the 9HIL
configuration without success (read: with many MEMORY LOST).
Moving all HP-IL to 9HIL free space for create new
Hepax RAM pages as HPX16 in place of the old two.
But I am not able to understand how make the Hepax
RAM pages accessible by two configurations
(One solutions is to keep my old configuration, but
I like so much the new MMU configurations created by Mr. Monte,
so, with your help, maybe I can make it !)
THANK YOU VERY, VERY MUCH!!!
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08-19-2019, 11:12 AM
Post: #17
RE: 41CL - DOUBLE HEPAX ACCESS
Please be patient, it's just that my free time is somewhat sparse at the moment.
The solution I am working will allow you to have multiple HePaX setup and will also allow you to save/restore HePaX RAM and MMU configuration to/from a HP-IL drive.
Sylvain
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08-19-2019, 11:36 AM
Post: #18
RE: 41CL - DOUBLE HEPAX ACCESS
Hi, It is not for impatience is also to give some data
of my config. You all help me very friendly!
I don't have any right to be impatient!
I have only to say thank you so much!
With best regards
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08-19-2019, 01:56 PM
Post: #19
RE: 41CL - DOUBLE HEPAX ACCESS
Just to be on the same page here, this article will review HePaX RAM configuration and 41CL MMU mapping.

References:
  1. 41CL Calculator Manual (sys41cl.pdf), revision 2019-06-22, chapter: HEPAX, pages 82 to 85

In this session we will:
  1. Copy HePaX RAM template from 41CL ROM to 41CL RAM pages (here: 0x821 to 0x824)
  2. Create the double link list binding these pages together (assuming final destinations 41OS port pages will be 0xC to 0xF)
  3. Mapping HePaX RAM & ROM
  4. Making a copy of the HePaX RAM (0x821 to 0x824) to another 41CL RAM area (0x831 to 0x834)
  5. Creating a data in the first HePaX RAM area (0x821 to 0x824)
  6. Swapping HePaX RAM areas (reconfiguring MMU configuration Set 0)

Ok let's do this ...

1) Copy HePaX RAM template from 41CL ROM to 41CL RAM pages (here: 0x821 to 0x824)
Code:
"0B9>821"  YMCPY      // copy HEPAX RAM template 0x0B9 to 41CL RAM page 0x821
"0B9>822"  YMCPY      // copy HEPAX RAM template 0x0B9 to 41CL RAM page 0x822
"0B9>823"  YMCPY      // copy HEPAX RAM template 0x0B9 to 41CL RAM page 0x823
"0B9>824"  YMCPY      // copy HEPAX RAM template 0x0B9 to 41CL RAM page 0x824

2) Create the double link list binding these pages together (assuming the final destination will be 41OS port pages 0xC to 0xF)
Code:
                      // in HePaX RAM page 1 (0x821) at 41OS port page 0xC,     previous page pointer is already set to 0x0 which mean begin/end of list
"821FE8-000D"  YPOKE  // in HePaX RAM page 1 (0x821) at 41OS port page 0xC, set next     page pointer to HePaX RAM page 2 (0x822) at 41OS port page 0xD
"822FE7-000C"  YPOKE  // in HePaX RAM page 2 (0x822) at 41OS port page 0xD, set previous page pointer to HePaX RAM page 1 (0x821) at 41OS port page 0xC
"822FE8-000E"  YPOKE  // in HePaX RAM page 2 (0x822) at 41OS port page 0xD, set next     page pointer to HePaX RAM page 3 (0x823) at 41OS port page 0xE
"823FE7-000D"  YPOKE  // in HePaX RAM page 3 (0x823) at 41OS port page 0xE, set previous page pointer to HePaX RAM page 2 (0x822) at 41OS port page 0xD
"823FE8-000F"  YPOKE  // in HePaX RAM page 3 (0x823) at 41OS port page 0xE, set next     page pointer to HePaX RAM page 4 (0x824) at 41OS port page 0xF
"824FE7-000E"  YPOKE  // in HePaX RAM page 4 (0x824) at 41OS port page 0xF, set previous page pointer to HePaX RAM page 3 (0x823) at 41OS port page 0xE
                      // in HePaX RAM page 4 (0x824) at 41OS port page 0xF,     next     page pointer is already set to 0x0 which mean begin/end of list

3) Mapping HePaX RAM & ROM
Code:
"%821 C"  PPLUG       // mapping HePaX RAM (4 pages) in 41CL RAM (0x821 to 0x824) to 41OS port page 0xC to 0xF
"HEPX B"  PPLUG       // mapping HePaX ROM (1 page 4 banks) to 41OS port page 0xB
HEPDIR                // validating HePaX RAM space, should show: "H:DIR EMPTY" press clear key (<-) then you should see in X: 2610.0000
At this point we have one HePaX setup with no data in HePaX RAM

4) Making a copy of the empty HePaX RAM (0x821 to 0x824) to another 41CL RAM area (0x831 to 0x834)
Code:
"821>831"  YMCPY      // copy 41CL RAM page 0x821 to 41CL RAM page 0x831
"822>832"  YMCPY      // copy 41CL RAM page 0x822 to 41CL RAM page 0x832
"823>833"  YMCPY      // copy 41CL RAM page 0x823 to 41CL RAM page 0x833
"824>834"  YMCPY      // copy 41CL RAM page 0x824 to 41CL RAM page 0x834
At this point we have two HePaX setup with no data in HePaX RAM (one active at 0x821 and one standby at 0x831)

5) Creating a data in the first HePaX RAM area (0x821 to 0x824)
Code:
HEPDIR                // should show: "H:DIR EMPTY" with 2610 in X, ok let create a file in HePaX so we differenciate the two HePaX RAM area
"TEST"                // HePaX data file name
20                    // HePaX data file size
HCRFLD                // create HePaX data file
HEPDIR                // should show: "TEST    DA        20" with 2588 in X
At this point we have two HePaX RAM area, one with data in it (0x821) and one empty (0x831) with the first area active (0x821)

6) Swapping HePaX RAM areas (reconfiguring MMU configuration Set 0)
Code:
"%831 C"  PPLUG       // activating second HePaX RAM area (0x831 to 0x834)
HEPDIR                // should show: "H:DIR EMPTY" with 2610 in X
"%821 C"  PPLUG       // activating first  HePaX RAM area (0x821 to 0x824)
HEPDIR                // should show: "TEST    DA        20" with 2588 in X
At this point we have proven that we can swap HePaX RAM area without any side effects.
You can only have one HePaX RAM area active at a time but with area swapping you can have a lot of data or program stored.

Finally, I have used the pages 0x821..0x824 and 0x831..0x834 to be easy to relate the steps with, but this setup does not use memory efficiently.
A more normal approach would have been to used these areas: 0x820..0x823, 0x824..0x827, 0x828..0x82B, 0x82C..0x82F, etc

Next article will finally address the backup and restore of HePaX RAM and MMU configuration.

Sylvain
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08-19-2019, 04:25 PM
Post: #20
RE: 41CL - DOUBLE HEPAX ACCESS
(08-19-2019 11:05 AM)Podalirius Wrote:  Hi, to say thank you so much seem to me very little for
all this help!!!!!!
It remain the problem with the Hepax module:
Is possible to install it twice?
The motivation is that my old configuration
has two Hepax RAM pages (HPX8) and also the HP-IL.
Now, with the new MMU configurations created by
Mr. Monte, the HP-IL settings resides on 9HIL and
with no space for Hepax. I tried to modify the 9HIL
configuration without success (read: with many MEMORY LOST).
Moving all HP-IL to 9HIL free space for create new
Hepax RAM pages as HPX16 in place of the old two.
But I am not able to understand how make the Hepax
RAM pages accessible by two configurations
(One solutions is to keep my old configuration, but
I like so much the new MMU configurations created by Mr. Monte,
so, with your help, maybe I can make it !)
THANK YOU VERY, VERY MUCH!!!

If you want to have your Hepax RAM to remain available when switching configurations, all you need to do is LOCK the pages containing the Hepax RAM before you load the new configuration. The MMU programming for Locked pages is never modified by a configuration change.
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