Hi all.
Even as the SR-56 featured four levels of subroutines, I would think that the SR-52 with 224 steps would benefit more from four levels of subroutines.
Remember that the SR-56 was introduced 9 months later, which may have given it some advantages over the SR-52 in some ways.
However, with limited memory capacity, everything is a trade-off. More memory registers or program steps? More built-in functions or pending operations or subroutine levels, etc. ?
Given that the SR-52's program steps were ** unmerged ** (GTO 123 took four steps, RCL 01 took three - that's 7 of the 224)... I'm not sure there were many programs written for the SR-52 that used up all three subroutine levels - would have to check the TI-PPC Notes if I had the desire to, but I really don't.
(rskey.org - go to the Library and you can download all the TI PPC Notes with tons of info).
The SR-56 had 100 steps and 10 data memories. Maybe that meant another subroutine level stored. Don't know.
The SR-56 had fewer than 64 op codes built in, making me wonder if it was a six-bit machine.
Intuitively, 4 subroutine levels seem enough for 224 steps.
In comparison, the HP-67 has only 3 subroutine levels:
https://www.hpmuseum.org/prog/hp67prog.htm
The TI-59 has 6 subroutine levels but it needs to deal with a much bigger addressing space (up to 100K steps, counting the module).
(05-28-2022 01:45 AM)pauln Wrote: [ -> ]Intuitively, 4 subroutine levels seem enough for 224 steps.
In comparison, the HP-67 has only 3 subroutine levels: https://www.hpmuseum.org/prog/hp67prog.htm
The TI-59 has 6 subroutine levels but it needs to deal with a much bigger addressing space (up to 100K steps, counting the module).
Yes a number of HP calculators also have 6 subroutine levels including the HP-34C and HP-41C. The HP-42S has 8 subroutine levels. The HP-32SII and HP 33s have 7 subroutine levels. The HP 35s has a whopping 20 subroutine levels!
Cool! Thanks for the chart.
(05-27-2022 11:07 PM)Gene Wrote: [ -> ]The SR-56 had 100 steps and 10 data memories. Maybe that meant another subroutine level stored. Don't know.
The SR-52 has two return pointers (from first-level subroutine to main program and from second-level subroutine to first-level subroutine). Assuming the return pointer is the step number to return to, this means 6 digits to store (2x3 digits).
As the SR-56 has only 100 program steps (00 to 99) the SR-52 6 digits return pointers can now store 3 return addresses (3x2 digits), so you get one more subroutine level with the same internal memory footprint.
(05-27-2022 11:07 PM)Gene Wrote: [ -> ]The SR-56 had fewer than 64 op codes built in, making me wonder if it was a six-bit machine.
I don’t think so. The SR-56 uses a single TMC0599 Multi-Register Chip which contains 30 registers (vs. two on the SR-52).
With 8-bit instructions the 100 steps fit in 13 registers (in fact 104 steps fit in 13 registers but the last 4 are not accessible due to the two-digit step number limitation).
Then you add 10 user memory registers which leaves 7 registers available for the 7 pending operations on the SR-56 (down from 10 on the SR-52).
With 6-bit instructions the 100 steps would fit in 10 registers and the SR-56 would have kept the 10 pending operations of the SR-52, but this would have meant a significant change on the memory program mapping logic to the memory registers and TI may have decided that it was not worth for 3 more pending operations on their entry level programmable calculator.
Good points, Didier! I had tried to count the different instructions and it seemed lower than 64.
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