|Some details on WROM within NoVRAM. (Somehow Long)|
Message #21 Posted by Diego Diaz on 24 May 2008, 3:24 p.m.,
in response to message #19 by PeterP
First a detailed (not too much) description on how NoVRAM handles WROM intruction.
Cycle: Time between two consecutive Phase0 pulses from Phi2. It always takes 56 pulses (bit time), about 155.55uSec @360KHz nominal NUT clock. Most instructions takes only one Cycle.
Phase: Every one of said 56 bit time between two consecutive Phi2 pulses counting from rising edge to rising edge of Phi2. Phases are numbered from Ph0 to Ph55. Phase duration is 2.77usec @360KHz
Phase0: (Ph0) First bit Phase. Inmmediatelly following the falling edge of SYNC signal on a Fetch Cycle.
Fetch: A Cycle in which NUT "fetches" its ROM (or MLDL RAM) to find next instruction to execute. SYNC line is hold high during Ph46 o Ph55 of a Fetch Cycle. ISA line sends the fetched Word during these 10 Phases.
c: NUT accumulator register. It holds 14 BCD digits in 14 nibbles, named c[13:0]. "c" register is sent on the DATA line at every Cycle starting at Ph02 Less Significant Bit first.
Word: 10bits going to be writen to or read from memory. WROM instruction takes its Word from "c" register bits 0 to 9, this corresponds with BCD digits c[2:0]. Note that the two last bits from c are not used.
Address: 16bits referring the memory position where the Word has to be writen to or read from. WROM takes its Address from "c" register bits 12 to 27. This corresponds with BCD digits [6:3]
WROM execution sequence on NoVRAM with HEPAX emulation as of Apr. '08 version.
NOTE: NoVRAM always reads both DATA Ph14 to Ph29 (c[6:3]) and ISA (Ph16 to Ph31) 16 bits addresses, and DATA Ph2 to Ph11 (c[2:0]) Word; and keeps them for every Cycle.
1. At some point, previous intructions must have placed the corresponding Address and Word into appropriate nibbles at "c" register.
2. NUT start a Fetch Cycle.
3. WROM (H'040) instruction is sent to NUT at ISA line Ph46 to Ph55 (i.e. at the *end* of this new Fetch Cycle). Word c[2:0] (Ph2-Ph11) and Address c[6:3] (Ph14-Ph29) have been sent by NUT but they won't be used as NoVRAM has no means to know that it's going to be a WROM until Ph55 finishes (In fact NoVRAM detects WROM at Ph11 during the following cycle). Consequently, both Word and Address will be read from the next Cycle.
4. NUT does nothing as WORM is a NOP. NUT keeps running and start another Fetch Cycle. Note that c register contents remains unaltered because NUT has only received and "executed" a NOP (H'040).
5. At Ph11 NoVRAM detects previous intruction was WROM and confirms it was a Fetch cycle. It reads Address from DATA Ph14 to Ph29 and sent it to its RAM.
6. As Ph26 to Ph29 (Address higher nibble) is read, NoVRAM checks if the received Address correspond to one of its own RAM pages and if that particular page has not been write protected by RAMTOG (H'1F0) instruction. If everything matches NoVRAM procceds with RAM write sequence and send the Word (which has also been read from DATA at Ph2 to Ph11) to the RAM chip during Phases Ph31 to Ph39. In case Address does not points to our RAM or RAM is write protected writting is aborted.
7. Due to the fact that RAM is writen during this Cycle (the following one to the WROM instruction) it is not possible to read from this RAM. Thus NUT will more likely receive a NOP (H'000) if the following Fetch Cycle points to RAM regardless what the next Address contents might be.
8. During the whole process DATA line is an input from NoVRAM's point of view. It doesn't send a bit at any moment.
The above description is consistent with the fact that WROM intruction should be followed by a NOP. But as far as I can see, does not explain how c[6:3] might be erased (or modified in any other way) by NoVRAM code. Mostly when, according to your last post, c[6:3] is zeroed regardless the number of NOPS you place before or after WROM instruction. Which leads me to another question: Is all of c register zeroed? or just c[6:3]. And yet another one for testing: What if you replace WROM with another NOP (H'000)? Obviously it won't write into RAM but, does it still erase c register?
Seems that we'll (I'll) have a lot of work ahead to find out what the h**k is cooking there... ;-)
Regarding the "battery eating" issue, it has nothing to do with NoVRAM operation. Excessive battery drain occured during Light and Deep Sleep, and was effectively fixed in the latest versions.
Best from Spain.
Edited: 24 May 2008, 3:43 p.m.