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[HP-35] MOS Circuit Development For The HP-35 - IEEE COMPCON72
04-29-2015, 11:00 PM
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[HP-35] MOS Circuit Development For The HP-35 - IEEE COMPCON72
The following article was presented at the IEEE COMPCON72 conference Sept. 12-14, 1972.

Thomas M. Whitney ___ Robert J. Paluc___
___Hewlett-Packard ___ Mostek Corporation
Palo Alto, California ___ Carrollton, Texas_

HEWLETT-PACKARD: Shortly after the HP 9100A calculator, was announced in March 1968, William Hewlett expressed a desire that the next design be one-tenth the volume and one-tenth the cost. After a trip to Japan in the summer of 1970 and a look at some of the portable four-function calculators being developed he reiterated his previous wish for a pocket size scientific calculator.

The challenge was presented to the corporate laboratories, where the original designers of the 9100 still resided. Work on an architecture was begun in October 1970 and a presentation on the feasibility made to management in February 1971. Although there were pressures to orient the calculator toward the large volume general business user, the final decision was to stick to the scientific market better understood by HP.

It was decided very early to have the custom MOS design done outside HP. Although we had some MOS experience internally, the high density, low power dynamic circuit design required had never been attempted. The company is often eager to take on challenges in technology, but the importance of a rapid, low risk development precluded an in-house source.

MOS Requirements
The MOS requirements were quite difficult. To achieve the required functional density we went to a totally serial design, which reduced interconnections both internal to the chip and between chips. However, the complex algorithms to compute transcendental functions require many multiplications, forcing a relatively high clock rate. We felt a 200 KHz bit rate could achieve the goal of a one second maximum computation time for any function. On top of the requirements for high density and high speed was the need for low power. The size and volume specification was set by Hewlett's shirt pocket; this meant few and small batteries. Four hours was set as the goal for calculator operating time.

In March 1971 we sent a request for quotations for a three chip system to seven vendors. At first a two chip partitioning was proposed but preliminary talks with vendors indicated at least three chips would be required. The request included complete logic drawings of the three circuits and some rough electrical specifications. Figure 1 shows a block diagram of the system.

MOS Proposal
MOSTEK: We received Hewlett-Packard's RFQ just after our announcement of having produced the first four function calculator on a chip. The request specified that the three chips were to be used in a "battery powered portable instrument”. Although we could guess from the logic diagram that the system had processor capabilities, we did not know what the final product was to be.

The three circuit types were the Instruction ROM, the Arithmetic and Register Chip, and the Timing and Control Chip. Table 1 is provided as an indication of the logic complexity and packaging requirement for each circuit. The electrical requirements stated that the system of chips be low powered and operate at 200 KHz. Although we could forsee individual problems in each circuit type, the major challenge would be in designing these complex chips to be low powered, and with chip sizes small enough to fit into the required packages.

To achieve low power dissipation in these logic arrays we planned to use appropriate circuit design, and our ion-implanted depletion P-channel process. This process, which Mostek pioneered, enable both low threshold enhancement mode devices, and depletion mode MOS devices to be integrated together on the same chip. The design engineer can take advantage of not only the characteristics of the enhancement mode device, but also highly efficient load devices using the constant current properties of the depletion device. Clever use of both these devices in a circuit design results in speed-power circuit performance 3 to 4 times superior to circuits designed using the standard P channel process. An additional system benefit of the "depletion" circuit is that it can be used with a low voltage, unregulated power supply.

To achieve the device packing density required of a three chip system, we planned to lay out each chip manually. Using this technique each transistor on the entire chip is manually drawn in a jigsaw puzzle manner taking advantage of surrounding layout conditions.

We invited the Hewlett-Packard design team to a meeting at Mostek to discuss our approach to the MOS development of the three chip system. We described a program plan and explained how our chips would meet the system’s requirements. A detailed layout plan of the Instruction ROM circuit was presented showing all the details of interconnect and blocks showing the location and area of each logic gate. Using this plan and a package bonding diagram, it was shown how this circuit could be built to fit in a TO-5 package.

The total power dissipation for the three chip system was estimated at 100 milliwatts using a 5 volt supply. Delivery of a set of ten prototype parts would take five months from receipt of contract.

Vendor Selection
HEWLETT-PACKARD: One of the requirements for vendor selection was that they have a low-threshold process in production. We also excluded several companies who had plans to market their own calculator since we were concerned with conflict of interest. Of the seven companies asked to quote, one company submitted a no-bid since the parts could never be offered to other customers, two companies said a three chip system was impossible and suggested a repartitioning into five chips, and four companies made valid quotations.

MOSTEK and AMI were selected on the basis of their past performance and our belief that the ion-implanted P-channel MOS process, which they both proposed, offered the most reliable technology to meet our specifications. Selecting two vendors gave initial insurance of rapid development, dual sources of parts later, and the hope that having vendors bidding against each other for production contracts would result in lower prices that would easily repay the double development cost.

The Program Plan
MOSTEK: After receiving notification that Mostek was one of the vendors chosen to produce the MOS chips for the HP-35 calculator, the proposed program plan was put into operation. The program under the direction of a program manager consisted of three concurrent projects: Design and Layout of the three MOS chips, construction of a hardware system simulator, and the construction of a computerized production tester.

Each circuit type was assigned to an MOS design engineer who assumed full responsibility for the circuit's logic, electrical and layout design, and eventually its transition into production. Under his direction was a layout designer who would translate the circuit configurations and transistor sizes into a 500 X drawing of the integrated circuit.

A hardware simulator of the HP-35 calculator was to be built to verify that the proposed MOS designs were not only logically correct but also capable of properly interfacing with the peripheral circuits. A Mostek systems engineer was assigned to understand the entire calculator operation and construct a node for node simulator, implemented using TTL logic elements. This breadboard would not only help insure system success, but also would be used to check out and characterize prototype parts.

Although the breadboard approach is well suited for engineering testings of MOS chips, it is far too cumbersome for the high volume testing requirements of production. To enable a rapid transition from prototype to production, the Mostek test equipment group began the design and construction of a PDP-11 computer controlled tester to perform the testing requirements for the three chips.

Generation of MOS Specifications
HEWLETT-PACKARD: Generation of meaningful specifications was a painful exercise for us since we had no experience with MOS circuits and we had very little feel for what could be achieved. In some instances MOSTEK wrote their desired specs and we made minor modifications where necessary. A major problem was in specifying the MOS to bipolar interface to our custom in-house display drivers.

The specifications are still changing slightly as the vendor determines through production experience which parameters can be relaxed and which should be tightened. In addition, HP has asked for some changes to accomodate some applications of the circuits to instruments (such as wider temperature limits). The specification interface requires a lot of compromise and a fundamental desire by both sides to find the lowest-cost, workable system.

Working Relationship Between Companies
HEWLETT-PACKARD: A contract was carefully written to cover the responsibilities and liabilities of both parties in the development effort. In actual fact, the contract was not very important to the success of the program. The flexibility and cooperativeness of the engineers at both companies are what make a program successful, and not anything in a contract.

One question which arose was how much MOSTEK should change the HP logic design. HP wanted MOSTEK to have flexibility to find the best design; yet HP had carefully simulated the logic with software and was concerned that major changes would both slow the program and perhaps introduce errors. This is a basic question in the vendor-customer relationship in an LSI design: should the vendor simply implement the customer's logic, or should he thoroughly understand it to the point where suggestions on improvements can be made. The advantages of complete understanding are apparent; a danger is that two engineers approaching the same design task will invariably find two different solutions, and which is "better" is not always obvious; while debate continues, time goes by.

MOS Design
MOSTEK: The first stage of design for the three calculator chips involved the revision of the original logic into a form which lended itself to MOS implementation. To reduce power, aid in minimizing layout, and meet timing specifications, propagation paths to output buffers were reduced, look ahead logic added to intrinsically slow paths, and various decoding and counter techniques were changed.

The next stage was to implement the logic into an electrical circuit. In addition to the design of the logic gates, flip-flops, and output buffers, several special circuits were developed. An internal clock generator which reduced chip area and improved circuit performance was designed to extend, attenuate, and regulate the externally supplied clocks. A new dynamic ROM approach was devised for the sequential state ROM in the timing and control chip to eliminate propagation delay. To enable both the random logic, and 400 bits of memory to be integrated together on one chip, a high packing density shift register was designed for the arithmetic and register chip. Several other novel circuits were also used such as single shots, delay strings, and level detectors.

The layout of each chip was begun after the logic was formulated and the majority of the circuit design complete. The details of each transistor and associated interconnections were drawn at 500 times final chip size. The result was a composite drawing of the 7 masks used in the MOS fabrication process.

From this composite the capacitive loading of each circuit node was calculated, and then device sizes adjusted to optimize power. After all the critical paths and individual circuit elements were simulated using our MOS transient analysis program, the composite was then ready to be used for generating the artwork for the actual integrated circuit. Table 1 lists the final chip sizes for each circuit type.

Hardware Simulator/System Schedule
HEWLETT-PACKARD: A trip was made to MOSTEK by the project manager in July 1971 to review the hardware simulator of the calculator. Of the three read-only-memories in the system, the one covering data entry and display was simulated along with the ASR and C&T circuits. The hardware worked perfectly and several problems in HP's software were detected.

The MOS design was the primary limiting factor in the calculator design cycle. Although there were several other critical "new technology" aspects to the calculator, including the multichip, plastic LED package, the low-power, high-current bipolar display drivers, the keyboard and the power supply, at the end we were waiting on MOS parts. Most of the other major parts of the calculator were manufactured internal to HP, where top priorities could be established and overtime authorized if necessary.

The First Chips
MOSTEK: The first Instruction ROM chips were completed four and a half months from the start of the program. A layout error found in the first parts rendered a section of logic inoperable. The necessary changes were made to the masks and a new run of material made. On the second try the circuit operated perfectly, with a power dissipation of only 3 milliwatts, a value 10 times less than was originally quoted. It was especially important that this design exhibit low power since it occurs several times in the system, each with different programming.

The first Arithmetic and Register chips were completed in September, 1971. These parts operated perfectly and met all the electrical specifications on the first run. The power dissipation for this circuit was 20 milliwatts, 10 milliwatts below the original estimate. The Arithmetic and Register circuit is in production today using masks made from the original master.

Several electrical and layout problems were encountered in the Timing and Control Circuit which required two additional iterations to repair. The breadboard simulator was used extensively during the check-out of this chip to "inject" and override internal erroneous signals that would mask possible problems in other selections of logic. The final revision of this circuit dissipates 50 milliwatts.

System Turn-On
HEWLETT-PACKARD: In our first prototype we had a mixture of parts from the two vendors. Fortunately the last MOSTEK part, the C&T circuit, was one of the first AMI parts. The system power was lower than we had specified allowing us to quote a worst case calculator operating time of five hours.

We found many errors in our first ROM programs, some of which were related to hardware. During design we used a software simulation of the system to evaluate the microprogramming. This simulation turned out not to be an exact duplication of the hardware. Fortunately the problems could be fixed by reprogramming . (Software saves hardware again !)

Other minor algorithm errors were later found so that we are now on the third pattern for each of our three ROMS. Turn-around on these patterns has been as fast as four weeks but 6-8 weeks is a safe time for planning purposes.

Production Chips
MOSTEK: The transition from shipping prototype quantities to large production quantities was marred by problems in getting the computerized tester checked out. Again the hardware simulator saved the situation by acting as a slow but thorough tester. By February 1972 the tester was in full swing for all five of the calculator chips, with shipment of the production quantities easily being met.

Gearing Up For Production
HEWLETT-PACKARD: The speed with which the HP-35 was developed, approximately one year from concept to production, was bound to create some problems. The usual production learning problems affected all parts, including the MOS vendors. Primarily, however, we failed to plan for the hugh success the HP- 35 has achieved. Orders have been three times the expected level, forcing a calculator delivery time which at one time was 12 weeks. Once the real demand for the HP-35 was realized it still took about 3-6 months to adequately increase the production.

Present Production
HEWLETT-PACKARD: Production is now running very smoothly, keeping up with the order rate. This high volume, low-cost instrument is a new business for HP, and necessity has made us learn very rapidly. In terms of customer response, the HP-35 is the most successful HP product ever introduced. The price is 1/10 that of the 9100, with 1/80 the volume. We are grateful to our MOS suppliers for the high quality, reasonably priced components which make it possible.

  1. The "Powerful Pocketful": An Electronic Calculator Challenges the Slide Rule, by Thomas M. Whitney, France Rode, and Chung C. Tung. Hewlett-Packard Journal, June, 1972.
  2. Implanted Depletion Loads Boost MOS Array Performance, by Bob Crawford. Electronics, Vol. 45, No. 9, pp. 85-90, April 24, 1972.
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