SR-52->HP-67 Keycodes efficiency

[Dieter]

(12-21-2017 02:59 AM)Matt Agajanian Wrote:  But, since there was no backward-compatability, why did TI hold to such a memory-hungry keycode system?

Memory hungry? If you want to store an instruction like "STO 01" there are two ways to do so:

1. Assign separate opcodes to each and every possible combination of command and parameter. For STO, RCL, SUM and PRD and registers 00-99 this alone means 400 (!) separate opcodes. While a single byte can hold 256. Now think of INV SUM, INV PRD and other commands like OP 00...40. Or GTO to dozens of different labels. Where does that end? Four bytes per opcode? Six?

This is the way the HP67/97 does it. But here there's just 10 registers for storage arithmetics, and not more than 15 labels.

2. Allow multiple byte instructions. This is how it is done in the HP41. Sure TI could have implemented a similar system. The TI59 standard memory configuration of 60 data registers and 480 program steps then would have meant, say, 200 or 250 merged steps – but of course with the same number of bytes as occupied by unmerged steps. It makes no difference whether "STO 01" takes one line or two.

BTW, take a look at the TI57. Here you can see merged steps in a TI calculator of the same era. But with merely 10 labels and just 8 data registers.

Dieter