HP67 running

[teenix]

...As always the devil is in the details, i.e.DATA line from CRC must be read with 180000 baud

I'm a bit confused at the transfer speed here unless I am missing something - which wouldn't surprise me :-)

I'm not sure how the read transfer is triggered from the CRC, but only CRC 100 and CRC 1700 are utilised for reading. It looks like CRC 100 is used to test the ready state of the buffer, and if not ready the CRC flag line = 1. I guess the flag line sets S3 directly in the Status Register. The CRC 100 commands are in a small count down loop that executes while S3 stays = 1. If the buffer is not ready when this counter wraps around an error condition occurs. When the buffer is ready to transfer, CRC 100 sets the CRC flag line = 0, clearing S3 and breaks out of the loop. Then CRC 1700 soon follows and seems to transfer the buffer data to register $9B or sets S3 = 1 if an error occurs.

I believe the data stream to/from the cards is about 1KHz with 28 bits of information made available for each transfer. It would therefore take about 28mS for the CRC to shift these into one of its buffers ready to go and this provides a time slot of 28mS for the PIC to read them while the next buffer fills.

A PIC running at say 16MHz would be able to execute 4000 instructions per bit. Even allowing 5% of the available processor time would give 200 instructions to process each bit. Shifting the new bit into a 56 bit memory register would take a minimum of 10 instructions which would take about 0.4uS, (1/70th of 1 bit time).

As the PIC would be controlling the Sync line, which I think clocks the CRC chip, transferring the data or issuing CRC commands and polling would just be part of its main loop.

The only polling required may be just the CRC flag line.

cheers

Tony