Question regarding HP41C Power Up Status circuit

[Jonathan Busby]

Well, it's been a long time since I've posted anything here. I think my last post was in early 2003, so that's about 15 years .

To get to the point, I've been looking for a circuit described in the HP41C technical hardware reference manual. Specifically, it's the Power Up Status OR "PUS" circuit in the 1LF6 chip. According to the manual "PUS uses a two threshold detection scheme coupled to a ratioed flip-flop designed to power up in a known state." I'd like to know how this circuit works but the manual says "Refer to the 1LF6 logic diagram for a full PUS circuit schematic." The only problem is that I've done a thorough search and I can't find said schematic. Does anyone know where the schematic is?

Thanks,

Jonathan