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HP 55 Internals

Posted by Tony Duell (UK) on 18 Sept 2003, 9:19 p.m.

Mechanical construction (and architecture) very similar to HP45 (see 
previous notes). 2 PCBs, keyboard and display on upper PCB, CPU and ROMs 
on lower PCB. Connections between PCBs by 28 pins

o-- Disp 0 o-- Disp 1 o-- o-- KC1 o-- Disp 2 o-- Disp 3 o-- Disp 4 o-- Phi_1 o-- Phi_2 o-- KC2 o-- Vbsw o-- Vcc o-- Gnd o-- Timer/ o-- PGM/ o-- RCD o-- KC3 o-- KR1 o-- KR2 o-- KR3 o-- KC5 o-- KR4 o-- KC4 o-- KR5 o-- KR6 o-- KR7 o-- o-- KR8

KC = Keyboard Column line. KR = Keyboard Row line Disp = display data bus from A&R chip to anode driver RCD = Reset Cathode Driver - start display scan Timer/ = connected to ground in 'Timer' mode PGM/ = connected to ground in PGM mode Phi_n = 2 phase system clock Vcc = 8.2V power line from PSU on logic board to cathode driver. Vbsw = switched battery voltage.

Keyboard/display PCB -------------------- There are 2 custom chips on the keyboard/display PCB.

1820-1029 (anode driver and system clock)

---------- Disp0 --| U |-- Ag Disp1 --| |-- Ae Disp2 --| |-- Ah Disp3 --| |-- Af Disp4 --| |-- Ad Step --| |-- Gnd Phi_1 --| |-- Ab Phi_2 --| |-- Ac LC --| |-- Aa Rset --| |-- Vbsw ----------

Disp = Display data bus (as above). A = display anode drive lines [1], segments named conventionally (h = decimal point) Phi_n = clock output to logic board Step = step output to cathode driver (display scanning) LC = Xtal from here to ground (~ 784kHz) Rset = resistor from here to ground, appears to be part of low battery circuit

[1] There's an inductor of 130uH (or 68uH for the point) from each anode line to Vbsw. Display runs from back-emf from these inductors. The HP55 uses 4-inductor hybrid modules rather than the discrete inductors used in earlier machines :

1810-0146

Ae---UUUUU---+ 130uH | | Af---UUUUU---+ 130uH | | Ah---UUUUU---+ 68uH | | Ag---UUUUU---+ 130uH | | Vbsw---------+ C

1810-0147

Aa---UUUUU---+ 130uH | | Ab---UUUUU---+ 130uH | | Ac---UUUUU---+ 130uH | | Ad---UUUUU---+ 130uH | | Vbsw---------+ C

1820-1226 cathode driver (essentially a 15 stage shift register for display scanning).

---------- k9 --| U |-- k8 k10 --| |-- k7 k11 --| |-- k9 Vbsw --| |-- k5 k12 --| |-- k4 k13 --| |-- Vbsw k14 --| |-- k3 RCD --| |-- k2 Step --| |-- k1 Vcc --| |-- k15 ----------

k = display cathode outputs. Step = display scan clock from anode driver RCD = Reset Cathode Driver = start scan (from A&R chip) Note lack of ground pin -- runs between Vcc (8.2V) and Vbsw (4V).

Logic PCB ---------

The 2 transistors and the transformer form a power supply giving the same 3 voltages (for the same purposes) as the HP35. There is no discrete component reset circuit, though (see below for what replaced it).

1820-1128 Clock driver and init ------- Init --| U |-- Init C --| |-- Phi_2 In --| |-- Phi_2 Out Gnd --| |-- Gnd --| |-- Vgg --| |-- Vss --| |-- Phi_1 In --| |-- Phi_1 Out -------

This replaces the 8 pin clock driver of the HP35 and most of the discrete components in the reset circuit. The signals are :

Phi_n In : 2 phase clock inputs from anode driver (at 'bipolar' levels) Phi_n Out (called Phi_n on other logic board chips) : 2 phase clock outputs to rest of CPU Init : Reset output to C&T and ROMs Init C : 2.2uF capacitor from here to ground -- reset timing capacitor. This is the only component in the HP35 reset circuit that couldn't be put on the chip.

Control & Timing (C&T) -- the control part of the CPU (and keyboard scanner) 1818-0078

---------- Vss --| U |-- WS Phi_1 --| |-- PGM/ Phi_2 --| |-- Timer/ Gnd --| |-- Sync Init --| |-- IA --| |-- Carry --| |-- KC1 KR2 --| |-- KC2 KR3 --| |-- KC3 KR4 --| |-- KC4 KR5 --| |-- KC5 KR6 --| |-- Vgg KR7 --| |-- KR1 KR8 --| |-- IS ----------

KC = Keyboard Column, KR = Keyboard Row (to keyboard matrix) Carry = Carry flag input from A&R chip Init = power-on reset IA = Instruction Address = address to ROMs IS = InStruction = ROM Data input Sync = machine cycle sync signal Phi = 2 phase clock WS = Word Select from ROMs (used to update part of a 56 bit word) PGM/ = pulled low in PGM mode (and pulled low via diode in timer mode) Timer/ = pulled low in timer mode

Arithmetic & Registers (A&R) -- CPU data path 1820-1169

---------- Phi_1 --| U |-- Phi_2 Vss --| |-- Gnd IS --| |-- Vgg Sync --| |-- Disp4 WS --| |-- Disp3 Carry --| |-- Disp0 Data --| |-- Disp1 RCD --| |-- Disp2 ----------

Disp = Display data bus. RCD = Reset Cathode Driver. Phi = 2 phase clock, IS = InStruction (from ROMs) Sync = machine cycle sync signal Carry = Carry flag output WS = Word Select Data = bit-serial contents of X (display) register.

1818-0118, 1818-00119, 1818-0120 : ROMs

Similar to the ROMs in the HP35, but presumably higher capacity. Now packaged in 16 pin DIL (ceramic) packages. The signals are the same as the HP35 ROM interface, and the pinout is :

------- Vss --| U |-- --| |-- IA --| |-- WS Gnd --| |-- Init --| |-- Phi_1 IS --| |-- Vgg Sync --| |-- Phi_2 --| |-- -------

See above for signal descriptions

1820-1393 RAM (3 used, address selected by SelA, SelB pins) This connects to the data pin on the A&R chip and transfers data to/from the arithmetic registers.

The pinout is : ------- Vss --| U |-- IS Gnd --| |-- Gnd --| |-- Data Gnd --| |-- Phi_2 SelB --| |-- Phi_1 SelA --| |-- Vgg Gnd --| |-- Gnd --| |-- RCD -------

Data : Data to/from A&R chip Phi_n : 2 phase clock inputs IS : ROM output (InStruction) line, used to address RAM. RCD : Reset Cathode Driver signal from A&R, used to define start of a word. SelA, SelB : Select address range for this RAM (both low on 1st RAM, Sel A connected to Vss on one of the other 2 RAMs, SelB connected to Vss on last RAM)

Testpoints ; There are 12 testpoints on the edge of the CPU board, in the same position and carrying the same signals as on the HP35. For reference, the signals are :

o-- Vss o-- Gnd o-- Phi_1 o-- Phi_2 o-- Vgg o-- IS o-- IA o-- Sync o-- WS o-- Init o-- Carry o-- Data

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