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HP28S: Hardware I/O basics

Posted by Christoph Giesselink on 19 June 2002, 12:23 p.m.

Content:

1. Fundamentals
2. HP28S memory layout
3. Master chip control registers
4. Slave chip control registers (only relevant)
5. Master display driver/timer registers
6. Slave display driver/timer registers
7. Display (used addresses)
8. Annunciators
9. Special considerations to master/slave operation

1. Fundamentals

The HP28S use 3 IC's: 2x Lewis 1LR2 chips, 1x 32KB RAM.

The Lewis chips work in master/slave configuration. Only in the master chip the CPU is running.

Each Lewis chip contain

the MMU and ROM is mask programmable, so the user can't change it's content. Having two Lewis chips the total amount of ROM is 128KB. The display memory is placed in each Lewis chip and is separated from the user memory in the external RAM chip.

2. HP28S memory layout

#00000 - #3FFFF 128KB ROM
#C0000 - #DFFFF 32KB RAM (mirrored)
#FF800 - #FFBFF slave display driver / timer
#FFB00 - #FFB0F slave control registers
#FFC00 - #FFFFF master display driver / timer
#FFF00 - #FFF0F master control registers

3. Master chip control registers

#FFF00 RATECTL          Rate Control (speed)
#FFF01 CONTRAST         Display contrast control
#FFF02 DSPTEST          Display test
#FFF03 DSPCTL           Display control + BIN
#FFF04 CRC              Crc (16 bit, LSB first)
#FFF08 LPD              Low Power Detection
#FFF09 LPE              Low Power detection Enable
#FFF0A MODE             Mode register
#FFF0B RAMTST           RAM test
#FFF0C INPORT           RX-LED pin state and service request
#FFF0D LEDOUT           Different modes for LED output
#FFF0E TIMER1_CTL       Timer1 control
#FFF0F TIMER2_CTL       Timer2 control

4. Slave chip control registers (only relevant)

#FFB03 DSPCTL           Display control + BIN
#FFB0E TIMER1_CTL       Timer1 control
#FFB0F TIMER2_CTL       Timer2 control

5. Master display driver/timer registers

#FFC00 - #FFE5F         Display area of master
#FFFF7                  Timer1 (4 bit)
#FFFF8 - #FFFFF         Timer2 (32 bit, LSB first)

6. Slave display driver/timer registers

#FF800 - #FFA5F         Display area of slave
#FFBF7                  Timer1 (4 bit)
#FFBF8 - #FFBFF         Timer2 (32 bit, LSB first)

7. Display (used addresses)

#FF840 - #FFB5F         Left display area
#FFC00 - #FFE27         Right display area

8. Annunciators

#FF800 - #FF807         Busy
#FF808 - #FF80F         Alpha
#FF810 - #FF817         Battery
#FF818 - #FF81F         Shift
#FF820 - #FF827         2*Pi
#FF828 - #FF82F         Halt
#FF830 - #FF837         Printer
#FF838 - #FF83F         All Annunciators

The contrast depends on the number of set bits, the more bits are set, the darker the annunciator is getting. The bits have no weight. At about 20 set bits you reach the darkest possible value.

Each bit of an annunciator address is XORed with the corresponding bit of "All Annunciators" to get the final number of set bits.

9. Special considerations to master/slave operation

"Master" mean: Register in master controller
"Slave" mean: Register in slave controller

Display

To turn on the display each controller must be turned on separately. The order is important, you must first turn on the slave then the master controller. Turning off should be done in reverse order, first the master then the slave controller.

Timer

The slave timer only run when the master timer is running. So switching off the master timer will also stops the slave timer.

Usage in the HP28S

Master Timer1 (16Hz)  : unused
Master Timer2 (8192Hz): tick counter
Slave  Timer1 (16Hz)  : unused
Slave  Timer2 (8192Hz): cursor blinking

The master timer is normally always running. Master Timer2 in connection with a 12 nibble value starting at #C0003 in user RAM builds a 1088 year counter (get the value with: # 11CAh SYSEVAL). The slave timer is normally stopped. Only at input mode with blinking cursor slave Timer2 is used to generate the blink frequency. That both Timer1 are unused has a historical background, the predecessor of the HP28S, the HP28C has only two 8192Hz hardware counter equal to the current Timer2.

Christoph Giesselink
cgiess@swol.de

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