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HP Forum Archive 19

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Meindert, guys: I think youre gonna like this!
Message #1 Posted by Vieira, Luiz C. (Brazil) on 22 Dec 2009, 5:45 a.m.

Hi, all;

I must confess I had some 'second thoughts' when asking information about the HP41 system ROM versions. With no further ado:

- I took a coconut mainboard and removed the three ROM IC's; everything else was kept in place
- The HP41CV was assembled and the MLDL2000 was set in place;
- Then I programed the MLDL2000 with a CX configuration: NFL ROM set + X-FCN + Time + CX time/FCN accordingly.

It worked flawlessly: an HP41CV with a CX configuration. Of course, no clock activity and no X-Memory present.

The key point is to keep the CPLD continuously powered. In fact, for as long as the USB is plugged and active (connected), the calculator goes OK. If it is simply disconnected by the software, the calculator no longer works because the CPLD is fed according to MLDLs J7 set (CPLD power control) or continuously through the USB port. I did not test yet, but if the CPLD is fed continuously through the HP41 batteries (J7: 1-2), the coconut may work with the MLDL2000 and without any ROM in the mainboard.

The good news is that you can use this arrangement to test your calculator and identify faulty ROMs. And you can use the MLDL2000 to emulate the faulty ROM. In any case, this is another way to have a faulty HP41CX coconut back to life if a ROM is missing.

Now I'll try a 41CV with no RAM ICs and point the first block address to a MLDL2000 SRAM 4K bank. I know that by simply pointing the first block address to a SRAM will cause address conflict, so Ill program the MLDL2000 to consider the SRAM as ROM. Yep, Ill check if the HP41 can 'see' a contiguous 4K-RAM bank, and if goes OK, then we will have all main and extended RAM at once through the MLDL2000.

Unfortunately there is no way to emulate both ROM and RAM at the same time in one single MLDL2000. The possible solutions are:

- keep ROM 0 chip in place and emulate the others;
- use two MLDL2000 (with a port extension, of course; not practical at all)
- convince either Meindert or Diego to provide such configuration trough either an MLDL2000 or a NoVRAM; this way one could run a 41CX (without a clock so far...) with external ROM/RAM.

Not a X-mas gift, instead some news to work with.

Cheers.

Luiz (Brazil)

Edited: 22 Dec 2009, 5:52 a.m.

      
Re: Meindert, guys: I think youre gonna like this!
Message #2 Posted by Meindert Kuipers on 22 Dec 2009, 11:56 a.m.,
in response to message #1 by Vieira, Luiz C. (Brazil)

Luiz,

You are the best! This is a configuration that I have thought of as a theoretical option, and now it becomes reality!

Replacing RAM IC's with the MLDL2000 will not work, as the MLDL2000 does not know how to emulate the RAM chips. This is not impossible to implement, and it is on my list of todo's and requires some pretty tricky coding of the CPLD, especially when it is mixed with ROM emulation. Also a second MLDL2000 will not help here.

The CPLD must be powered when the HP41 starts. The reason is that the CPLD cells must be loaded from internal EEPROM cells, and that takes up to 200 microseconds after powerup. During this time the CPLD will not respond to any HP41 cycles. I have new CPLD firmware with reduced the power that could be used for this. A possibility could be a modified ROM 0 to compensate for the fact that the CPLD starts slower than the HP41. Replacing the first two words in ROM 0 with NOP should actually do it, but then the HP41 would always do a DSWKUP, which would probably mess up the partila key sequencing. More work to try out for you Luiz!

I have some time during the Christmas holidays to play with this myself, although I will not remove any ROMs form any of my precious 41's.

Meindert

            
Re: Meindert, guys: I think youre gonna like this!
Message #3 Posted by Vieira, Luiz C. (Brazil) on 22 Dec 2009, 12:30 p.m.,
in response to message #2 by Meindert Kuipers

Hi, Meindert;

thanks for your feedback. I aprreciate it! (being called the best by the best... 8^) I'm flattered!)

For the records: this HP41 mainboard had some issues, and I was almost sure they were related to a faulty ROM. It seems to me I was right...

Now for the mistakes. Please, replace the text:

Quote:
Now I'll try a 41CV with no RAM ICs and point the first block address to a MLDL2000 SRAM 4K bank. I know that by simply pointing the first block address to a SRAM will cause address conflict, so Ill program the MLDL2000 to consider the SRAM as ROM.
for the text:
Quote:
Now I'll try a 41CV with no RAM ICs and point its first I/O block address to a MLDL2000 SRAM 4K bank. I know that by simply pointing the first block address to a SRAM will cause address conflict, so Ill program the MLDL2000 to consider the SRAM as I/O.

I messed up terminology and components big time! I wrote that text at 5:45AM after being working all night with many subjects. I tested the MLDL2000 configuration at 5:00 AM because I needed a break, so this was my 'relaxing activity'. Sorry!

Now lets see: if the HP41 uses I/O addressing to access RAM chips, and the I/O uses an 8-bit wide data pattern (one byte), this is the very organization you provided the MLDL2000 with, right? Why not to address one of the MLDL2000 SRAM blocks as I/O in the first I/O address range? This is were the main RAM is addressed in the HP41, right?

I surely need to read and reason a lot more prior to jump into conclusions, but I'll do that carefully. No rush...

Cheers.

Luiz (Brazil)

Edited: 22 Dec 2009, 12:53 p.m.

                  
Re: Meindert, guys: I think youre gonna like this!
Message #4 Posted by Meindert Kuipers on 22 Dec 2009, 2:21 p.m.,
in response to message #3 by Vieira, Luiz C. (Brazil)

I will not comment on the other remarks ;) Today is my wife's birthday, so I will be signing off and have a glass of wine.

To be precise,the HP41 RAM registers are addressed not as I/O but as a peripheral with RAMSLCT, so it will respond to READ and WRIT instructions. The MLDL2000 ignores these instructions, and this is not to be confused with the I/O as defined in the MLDL2000, which is simply a set of I/O registers mapped in ROM space. The HP41 RAM registers use a 56 bit serial datapath, and the information is transferred through the DATA line. The MLDL2000 can read the DATA line, but not write to it, although hardware circuitry is there to support it, the functionality is simply not implemented in the CPLD. Again, this type of useage is anticipated, but not (yet) implemented.

Keep up the good work!

Meindert

                        
OK, then!
Message #5 Posted by Vieira, Luiz C. (Brazil) on 22 Dec 2009, 3:44 p.m.,
in response to message #4 by Meindert Kuipers

Thanks again, Meindert. You have already mentioned these facts at the MLDL2000 Specifications, I mean, the ability of reading but writing to the DATA line. I forgot about that.

Time to put the system ROM images in SRAM and picking on them. Now we can go ahead messing up with the HP41 O.S. and hacking it from the core... Does it make the HP41 a 'repurposeable' development platform?

Cheers.

Luiz (Brazil). 'Roger and out'!

Oops! Forgot to wish your wife my best!

Edited: 22 Dec 2009, 3:48 p.m.


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