HP Forum Archive 18

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HP-71b memory / chip select access - How is it done? Message #1 Posted by peter a walker (papwalker) on 25 Aug 2008, 1:46 a.m. Looking at the schematic in the IDS I can't for the lide of me work out how the memory is addressed. There doesn't seem to be enough lines on the HP-71b bus. peter walker

Re: HP-71b memory / chip select access - How is it done? Message #2 Posted by Eric Smith on 25 Aug 2008, 1:04 p.m., in response to message #1 by peter a walker (papwalker) The four operating system ROM chips (32K*4 each), three display driver chips (each including 1K*4 RAM), and the optional card reader all are configured to fixed addresses. The rest of the built-in RAM, and all of the normal plugin modules (ROM, RAM, HP-IL, etc) are "soft-configured", which means that their addresses are assigned dynamically. The soft-configuration process uses a daisy chain (DI and DO signals), so that a device will only respond to the configuration command when it is not already configured and its DI line is active. Initially its DO line is inactive, but once it is configured the DO line becomes active so that the next device in the daisy chain can be configured. There are actually six daisy chains in the 71B, driven by CPU output port pins. IIRC, five are for ports (including the HP-IL port), and one is for the internal RAM and the card reader port. The bus is multiplexed, so addresses are sent over the same four-bit bus as data. The C/D line indicates whether the data bus contains "commands" or data. Commands include sending an address, starting a read or write, identifying, configuring, or unconfiguring soft-configured devices, etc. This is all covered in the IDS. The software IDS volume 1 gives a high-level overview, and the hardware IDS gives the electrical details.

Re: HP-71b memory / chip select access - How is it done? Message #3 Posted by peter a walker (papwalker) on 26 Aug 2008, 10:07 a.m., in response to message #2 by Eric Smith I'm still waiting for the complete IDS via the museum DVD. If I understand you correctly, the addressing and or other functions are *serialized* on the bus in that a 4 bit command may be followed by several 4 bit data 'packets'. Time / contect division multiplexing. They used a protocol on the bus! I must admit the idea never occurred to me for memory addressing but since it's the same bus as for other 'peripherals' it's the logical way to go. I've been infected by Rockwell and Intel. I'm impressed. Thanks for the insight. .

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