|Re: HP25 Memory|
Message #7 Posted by Tony Duell on 6 Dec 2005, 2:44 p.m.,
in response to message #4 by Grahame Sutherland(Scotland)
Here's a little background. Some of this comes from what I know about the HP41 series (NUT CPU), I believe the Woodstocks (ACT CPU) are similar, but hopefully Eric Smith will correct any serious errors.
The bus in these machines is bit serial. There's a 2 phase clock generated by the ACT which is routed to all the chips, there are 56 clock cycles per machine cycle. The ACT also generates a SYNC signal during a particular set of clock states of _most_ machine cycles (yes I believe I know the reason for this, but I don't want to confuse you too much).
Another bus line is ISA (Instruction and Address). During the first part of a machine cycle, the ACT outputs a ROM instruction address bit-serially on this line. During a later part of the cycle -- actually the states where SYNC is asserted, the ROM outputs the instruction, again bit-serially, and it's read by the processor _and by other chips in the machine_.
The last bus line you need to consider is the DATA line. This is normally an output from the ACT, and carries the 56 bits (one bit per clock cycle) from one of the internal registers of the ACT.
The RAM chip connects to all those bus lines and very little else. There is, for example, no traditional Read/Write line or address bus to the RAM.
To store something in RAM, the ROM chip contains a write-to-RAM instruction. To the ACT processor this is essentially a NOP. But the RAM also decodes it, and on the next machine cycle stores the bits from the DATA line into one of the 56 bit RAM 'registers'.
To load something from RAM, the ROM outputs a read-from-RAM instruction. Now the processor makes the DATA line an input, and stores the 56 bits presented on it during the next cycle into the appropriate register. Meanwhile the RAM also decodes that instruction and outputs the selected 56 bit 'register' onto the DATA line.
From this you can see that the RAM chip in an HP25 is a lot more than just RAM. It includes circuitry to decode some of the machine code instructions and do the appropriate things.