Re: Opcodes Message #4 Posted by Eric Smith on 19 July 2004, 4:01 p.m., in response to message #3 by Klaus
While the original 1818-0012 CTC chip probably did clear the status bits as expected from the patent description for any instruction xxxx110100, the later 1818-0078 must have ignored the instruction if the top four bits were nonzero. The "delayed select rom n" and "delayed select group n" instruction do in fact use these encodings.
The HP-35, HP-45, and HP-80 do not use the "delayed select" instructions, and have been seen with either CTC chip. The HP-55 and HP-65 use the "delayed select" instructions, and I have only ever seen the 1818-0078 CTC chip in those models. I am not sure whether the HP-46, HP-70, HP-81, and HP 1722A use any "delayed select" instructions, but I suspect that they are used in the HP-70 and not in the others.
I probably noticed this feature of the instruction encoding when I originally wrote CASMSIM back in 1995, but had since forgotten about it.
The HP-35, HP-45, and HP-80 ROMs do not contain any "clear status" instructions with non-zero top four bits, so it is acceptable to only simulate the behavior of the later CTC chip.
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