|About Bank Switching, RAM/ROM-Boxes, MLDL, HEPAX... and so on.|
Message #2 Posted by Diego Diaz on 23 July 2003, 6:03 p.m.,
in response to message #1 by Meindert Kuipers
Hi Meindert, folks,
First of all I must say I've been following your MLDL2000 work since the beginning, I have no microcontroller experience at all so I can't be of any help for you in that sense.
Anyhow, I'm quite handy with wires & chips (IC's... well... and fried potatoes also ;-) BTW I've just finished my own (breadboard-prototype) ROM Box, starting from the original Lynn A Wilkins MLDL as published in PPCJ V9N3.
I've done some modifications:
- As I was not interested in the RAM area, I rub the related components off.
- 2732 & 2716 pairs might be a good solution with '82 eyes, but nowadays, EPROM's are more easily found in bigger capacities and those older models are scarcy and non price competitive.
- Further more, the 10bit 41's word implementation in the original MLDL was extremely complex with 2 last bits (MSB's) multiplexed into an 8bit 2716 word for every four 2732 word... !? Well I simply place the 10 bits into two consecutive words of a 2764 or 128 or 256 or 512 (the last gives you the full 32k-words available for the 41's four extension ports) then read the Least Significant Byte from the odd address, send them to the ISA line, and at the proper time read the remaining two bits from the even address. So one only shift register is needed to drive the ISA line output and one only EPROM is needed to hold the "module" (or modules) data. Yes, you throu 6 bits away for each word but who cares?
- Several other minor "improvements" regarding the state counter and some gates saved here and there, and the whole thing is working.
Sorry, up to here I'm pretty sure I've told you nothing new, but I'm willing to share my experience so other can see that there is no mystery in bulding an (EP)ROM-Box for the 41.
Up to this point I've not implemented the bank switching capability for that, mainly because I have not a full knowledge about the way it works, but I've been doing my homework and here you are what I've found out:
- Bankswitching instructions ENBANK1, 2, 3 & 4 ($100, $180, $140 & $1C0 respectively) are NOP's for the 41 mainframe OS.
- Wichever module's willing to handle with them must reserve some specific memory addresses for the RETURNing, namely $XFC7, $XFC9, $XFCB & $XFCD (X beeing the hex value for the address four MSb's.
This MUST be present in every 4k bank of the module.
Obviously if a module is only going to handle Banks 1 & 2 it has no need to implement the corresponding returnings for Banks 3 & 4.
- Once the swithching has been performed, is in the internal module electronics in wich the responsibility of handling it relays, so the enabled bank is the one that can be seen at this specific 4k address area. This is why you can (e.g. in the HEPAX) relocate the address the module responds at, and override the "hardwired" B3 & B4 address lines to the I/O ports.
Remember this is an "at first glance" approximation of the bankswitching behavior, I've got a lot to learn about it yet and, of course, it may not be accurate in some points, so take it AFAIK and excuse me for the possible mistakes.
Some others out there sure can enligthen us with a deeper knowledge regarding this issue.
Cheers from the Canary Islands.