Re: Woodstock ACT Instruction Set
Message #3 Posted by Michael F. Coyle on 31 May 2003, 12:00 a.m.,
in response to message #2 by Renato
Hi Renato,
First, let me describe how I've spent the last three weeks.
I bought an HP-21 on eBay and received it May 10. I spent a couple of days playing with it and charging up some batteries. I then took it all apart and hooked it up to my test equipment. It's been that way ever since.
I have the HP-21 schematic that's been floating around here for a while. I've been using an oscillscope to look at the various signals coming off the chips and I've produced a detailed timing diagram (similar to what's in the HP-97 servide manual but more detailed).
The most interesting signal is the one that carries addresses and data to and from the ROM. I can look at the signals and read some of the bits but the instructions don't match up well to the Classic instructions, as far as I can tell. In particular, addresses have been widened to 10 bits from 8 and some instructions, branches at least, take two words in memory.
My 'scope has analog storage and delayed sweep, so I can sometimes trigger on a repetitive instruction sequence and read off all the addresses and data; it's pretty tedious though. Here's an example of what I have: the idle loop (waiting for a key to be pressed) is apparently a single instruction, two words long:
Addr Data My Interpretation
---- ---- -----------------
254 1111011100 (Probably: If no key pressed, goto...)
255 0011111110 (254)
SYNC is asserted during the data read-in at location 254 but not at 255, as we'd expect from a two-word instruction. (By the way, the bits are presented on the bus LSB first; I've reversed the back to their "right" order in the example.)
I'll throw in the other piece of code I have information for: the other part of the idle loop, which runs after your function has been executed but while your finger is still holding down the button. (In other words, it's waiting for you to lift your finger so that it can resume the scan listed above.)
Addr Data My Interpretation
---- ---- -----------------
246 1111001100 (Old CPU: 15->p)
247 0010111100 ???
248 0110010000 (Old CPU: Select ROM 3)
249 1011101100 (Old CPU: If p # 11)
250 0011111000 (248)
251 1111010100 (Probably: If key still down, goto...)
252 0011110110 (246)
The instructions listed as "Old CPU" are probably wrong for the ACT. What actually happens is that the instructions at 246 and 247 initialize a loop, probably a debounce delay. The instructions from 248 to 250 are executed 7 times in the loop. (The delay would be about 7 ms.) After the loop, there is probably a test that says, if the key is still being held down, then jump back up to 246 and do another delay. If the key was lifted, the CPU presumably executes a one-word instruction at location 253 (I haven't seen that one yet), then waits in the one-instruction loop at 254 and 255.
I've stopped looking at the moment because this is about as far as I can get get with the equipment and knowledge I have. I could build a special piece of hardware to automatically grab the addresses and data on the bus but without better information on the instruction set and opcodes, there's not much point.
If any of the HP engineers who worked on these chips or calculators are lurking on this Forum, now would be a good time to speak out!
Comments, etc. always welcome.
- Michael
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