|HP41 ROM/RAM box status update (long)|
Message #1 Posted by Meindert Kuipers on 25 Oct 2002, 4:48 a.m.
Let me give you a quick update on the current status of the MLDL2000 development project. In addition I have a few questions for the community that I would like to have some feedback on.
I have now completed the first phase of MLDL2000, which is a full functional simulation of a 'Classic ROMBox'. There is no hardware yet, but I am about to purchase a Xilinx CPLD prototyping board and start building some real hardware. The updated design (VHDL files) is at www.kuipers.to/hp41 together with a view of the simulation results and testbench (this information is now all under the GNU license). This part is ROM only, and was done to prove that the concept would work and to get myself up to speed with the HP41 interface and the VHDL language.
The device used is a Xilinx Coolrunner XPLA3 CPLD with 64 macrocells, and I am using about 60% of its resources. As I expect that the number of registers will go up dramatically when the data shift register is implemented I hope that in the final MLDL2000 everything will fit in a 128 macrocell device, but that will be pretty tight. The next step is a 256 macrocell device (which is on the prototyping board I am considering) and that will be more than enough.
The main problem I am facing is that I do not need many I/O pins, but rather a lot of registers and macrocells. But devices with more macrocells have more I/O pins anyway, and are physically larger.
I am now working on the next step: use one EPROM only, with use of the Settings Registers. This requires 3 cycles to get EPROM data and makes the state machine more complicated, but will reduce power consumption and number of parts (1 EPROM only). I expect that this will be implemented in hardware for debug. The Bank Switching will be part of this device as well.
I have also started to work on the schematic. I have to learn the program (Eagle CAD, which has a free version at www.cadsoft.de) and build libraries, as none of the parts I intend to use are in there. But I could use some help in making the schematic (and layout in a later stage).
Following will be expansions with MLDL RAM and an interface to a PC. I do not know exactly how to do the PC interface yet, but most likely it will be using the parallel port to exchange data. At the same time Flash programming needs to be implemented.
I will update the specifications to reflect larger Flash EPROM (2 or 4 instead of 1 Mbit) and larger SRAM (size not yet known). I am looking for a volunteer to make a set of basic functions to manage the MLDL2000. I am considering to define a new peripheral to control the MLDL2000. Any comments?
The following functionality needs to be managed:
- direct access to the Flash Eprom and SRAM
- I/O to and from the PC interface
- Switching, enabling/disabling/write protecting ROM/SRAM banks
- Flash programming
What about the name? I have now been using MLDL2000, but it is much more than that. Any suggestions?
One of the better ways to communicate as a development community is a mailing list. Let me know if you like the idea and I will set it up (my provider has the facilities to setup a mailing list through my domain at kuipers.to).
Continue with your valuable feedback!